Simulation Results: edn/edn0

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.65 %
  • code
  • 77.35 %
  • assert
  • 95.23 %
  • func
  • 78.37 %
  • line
  • 95.60 %
  • branch
  • 86.33 %
  • cond
  • 81.54 %
  • toggle
  • 80.27 %
  • FSM
  • 43.01 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.090s 110.971us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 53.915us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 14.998us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.800s 359.171us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.060s 23.938us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.180s 110.620us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 14.998us 1 1 100.00
edn_csr_aliasing 1.060s 23.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.480s 65.222us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.480s 65.222us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.480s 65.222us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.200s 31.912us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.020s 22.659us 1 1 100.00
errs 1 1 100.00
edn_err 1.410s 37.733us 1 1 100.00
disable 1 2 50.00
edn_disable 0.930s 20.850us 1 1 100.00
edn_disable_auto_req_mode 2.940s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 1.700s 282.819us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.220s 21.071us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 14.968us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.670s 150.210us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.670s 150.210us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 53.915us 1 1 100.00
edn_csr_rw 0.840s 14.998us 1 1 100.00
edn_csr_aliasing 1.060s 23.938us 1 1 100.00
edn_same_csr_outstanding 1.190s 40.309us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 53.915us 1 1 100.00
edn_csr_rw 0.840s 14.998us 1 1 100.00
edn_csr_aliasing 1.060s 23.938us 1 1 100.00
edn_same_csr_outstanding 1.190s 40.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.400s 326.877us 1 1 100.00
edn_tl_intg_err 1.960s 122.837us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.060s 50.980us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.020s 22.659us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.400s 326.877us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.400s 326.877us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.400s 326.877us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.400s 326.877us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.020s 22.659us 1 1 100.00
edn_sec_cm 4.400s 326.877us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.020s 22.659us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.960s 122.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 65.720s 32155.732us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 55087366961960475328606654084768396685646268020150808185562887360070491138 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---