Simulation Results: entropy_src/rng_16bits

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 68.50 %
  • code
  • 82.70 %
  • assert
  • 72.80 %
  • func
  • 50.00 %
  • block
  • 94.34 %
  • line
  • 98.03 %
  • branch
  • 86.42 %
  • toggle
  • 52.60 %
  • FSM
  • 93.75 %
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 20.941us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 3.000s 114.422us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 23.827us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 11.000s 518.046us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 62.852us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 3.000s 104.394us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 23.827us 1 1 100.00
entropy_src_csr_aliasing 4.000s 62.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 20.941us 1 1 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
entropy_src_fw_ov 91.000s 13340.394us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 91.000s 13340.394us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 130.000s 14097.518us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
entropy_src_intr 13.000s 2062.968us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
entropy_src_functional_alerts 5.000s 175.090us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 85.000s 13955.771us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 110.935us 1 1 100.00
firmware_ov_read_contiguous_data 0 1 0.00
entropy_src_fw_ov_contiguous 1.000s 26.248us 0 1 0.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 13.814us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 30.005us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 36.001us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 36.001us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 114.422us 1 1 100.00
entropy_src_csr_rw 2.000s 23.827us 1 1 100.00
entropy_src_csr_aliasing 4.000s 62.852us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 49.215us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 114.422us 1 1 100.00
entropy_src_csr_rw 2.000s 23.827us 1 1 100.00
entropy_src_csr_aliasing 4.000s 62.852us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 49.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 4.000s 182.764us 1 1 100.00
entropy_src_tl_intg_err 4.000s 95.326us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
entropy_src_cfg_regwen 2.000s 60.292us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
entropy_src_fw_ov 91.000s 13340.394us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 110.935us 1 1 100.00
entropy_src_sec_cm 4.000s 182.764us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 110.935us 1 1 100.00
entropy_src_sec_cm 4.000s 182.764us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 293.000s 14018.716us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 110.935us 1 1 100.00
entropy_src_sec_cm 4.000s 182.764us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 110.935us 1 1 100.00
entropy_src_sec_cm 4.000s 182.764us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 110.935us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 175.090us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 95.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 287.000s 13028.771us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (entropy_src_scoreboard.sv:2126) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.observe_fifo_depth
entropy_src_fw_ov_contiguous 106789499870752053460421674032822276417575435529784725524855306238069511403685 159
UVM_INFO @ 26247623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---