Simulation Results: hmac

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.61 %
  • code
  • 98.48 %
  • assert
  • 96.70 %
  • func
  • 43.64 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 96.35 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 12.380s 5794.201us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.970s 24.484us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.810s 26.831us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.420s 2316.081us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.150s 399.365us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.310s 143.859us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.810s 26.831us 1 1 100.00
hmac_csr_aliasing 4.150s 399.365us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 43.490s 3065.758us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 7.440s 159.985us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.880s 659.194us 1 1 100.00
hmac_test_sha384_vectors 20.700s 224.442us 1 1 100.00
hmac_test_sha512_vectors 20.680s 3304.497us 1 1 100.00
hmac_test_hmac256_vectors 7.390s 942.363us 1 1 100.00
hmac_test_hmac384_vectors 7.040s 451.988us 1 1 100.00
hmac_test_hmac512_vectors 10.990s 1259.886us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 21.490s 984.406us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 228.510s 19779.450us 1 1 100.00
error 1 1 100.00
hmac_error 12.190s 268.618us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 58.530s 4198.251us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 12.380s 5794.201us 1 1 100.00
hmac_long_msg 43.490s 3065.758us 1 1 100.00
hmac_back_pressure 7.440s 159.985us 1 1 100.00
hmac_datapath_stress 228.510s 19779.450us 1 1 100.00
hmac_burst_wr 21.490s 984.406us 1 1 100.00
hmac_stress_all 909.770s 38132.388us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 12.380s 5794.201us 1 1 100.00
hmac_long_msg 43.490s 3065.758us 1 1 100.00
hmac_back_pressure 7.440s 159.985us 1 1 100.00
hmac_datapath_stress 228.510s 19779.450us 1 1 100.00
hmac_wipe_secret 58.530s 4198.251us 1 1 100.00
hmac_test_sha256_vectors 8.880s 659.194us 1 1 100.00
hmac_test_sha384_vectors 20.700s 224.442us 1 1 100.00
hmac_test_sha512_vectors 20.680s 3304.497us 1 1 100.00
hmac_test_hmac256_vectors 7.390s 942.363us 1 1 100.00
hmac_test_hmac384_vectors 7.040s 451.988us 1 1 100.00
hmac_test_hmac512_vectors 10.990s 1259.886us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 12.380s 5794.201us 1 1 100.00
hmac_long_msg 43.490s 3065.758us 1 1 100.00
hmac_back_pressure 7.440s 159.985us 1 1 100.00
hmac_datapath_stress 228.510s 19779.450us 1 1 100.00
hmac_burst_wr 21.490s 984.406us 1 1 100.00
hmac_error 12.190s 268.618us 1 1 100.00
hmac_wipe_secret 58.530s 4198.251us 1 1 100.00
hmac_test_sha256_vectors 8.880s 659.194us 1 1 100.00
hmac_test_sha384_vectors 20.700s 224.442us 1 1 100.00
hmac_test_sha512_vectors 20.680s 3304.497us 1 1 100.00
hmac_test_hmac256_vectors 7.390s 942.363us 1 1 100.00
hmac_test_hmac384_vectors 7.040s 451.988us 1 1 100.00
hmac_test_hmac512_vectors 10.990s 1259.886us 1 1 100.00
hmac_stress_all 909.770s 38132.388us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 909.770s 38132.388us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 15.414us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.640s 52.084us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.640s 89.861us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.640s 89.861us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.970s 24.484us 1 1 100.00
hmac_csr_rw 0.810s 26.831us 1 1 100.00
hmac_csr_aliasing 4.150s 399.365us 1 1 100.00
hmac_same_csr_outstanding 2.030s 163.551us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.970s 24.484us 1 1 100.00
hmac_csr_rw 0.810s 26.831us 1 1 100.00
hmac_csr_aliasing 4.150s 399.365us 1 1 100.00
hmac_same_csr_outstanding 2.030s 163.551us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.840s 76.494us 1 1 100.00
hmac_tl_intg_err 2.980s 308.886us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.980s 308.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 12.380s 5794.201us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.890s 280.024us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 40.500s 2845.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.890s 7.515us 1 1 100.00