Simulation Results

Simulation Results: i2c

27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.66 %

code
81.40 %

assert
96.19 %

func
79.39 %

line
96.38 %

branch
92.33 %

cond
85.01 %

toggle
89.24 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	45.190s	5594.536us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	12.080s	6193.299us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.950s	27.203us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.780s	25.383us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.100s	528.739us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.200s	432.128us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	44.546us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.780s	25.383us	1	1	100.00
	i2c_csr_aliasing	1.200s	432.128us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	3.400s	398.486us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	212.220s	9305.773us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	263.370s	6952.223us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.820s	90.337us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	56.890s	7402.121us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	61.670s	7720.044us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.980s	177.830us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.140s	270.976us	1	1	100.00
	i2c_host_fifo_reset_rx	6.780s	161.143us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	50.340s	8881.994us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	10.380s	294.425us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.680s	6.338us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.080s	453.220us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	16.630s	4860.137us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.360s	4497.168us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	13.910s	3919.479us	1	1	100.00
	i2c_target_intr_smoke	4.840s	5147.337us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.340s	211.701us	1	1	100.00
	i2c_target_fifo_reset_tx	1.620s	278.579us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	23.380s	15940.967us	1	1	100.00
	i2c_target_stress_rd	13.910s	3919.479us	1	1	100.00
	i2c_target_intr_stress_wr	35.260s	23291.276us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.190s	2671.145us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	10.230s	10018.782us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.120s	1514.424us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.480s	1824.635us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.850s	483.098us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.990s	98.190us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	263.370s	6952.223us	1	1	100.00
	i2c_host_perf_precise	23.330s	791.902us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	10.380s	294.425us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	5.380s	278.382us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.030s	459.839us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.080s	1208.363us	1	1	100.00
	i2c_target_nack_txstretch	1.250s	263.211us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.580s	270.302us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.880s	464.009us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.990s	15.393us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.870s	18.903us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	0.890s	126.093us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	0.890s	126.093us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.950s	27.203us	1	1	100.00
	i2c_csr_rw	0.780s	25.383us	1	1	100.00
	i2c_csr_aliasing	1.200s	432.128us	1	1	100.00
	i2c_same_csr_outstanding	1.160s	26.784us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.950s	27.203us	1	1	100.00
	i2c_csr_rw	0.780s	25.383us	1	1	100.00
	i2c_csr_aliasing	1.200s	432.128us	1	1	100.00
	i2c_same_csr_outstanding	1.160s	26.784us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.640s	96.145us	1	1	100.00
	i2c_sec_cm	1.110s	147.413us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.640s	96.145us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	20.540s	5972.558us	1
target_error_intr				1
	i2c_target_unexp_stop	1.120s	109.339us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	6.280s	504.712us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	60778927197511583861314151466490613181955610487476694321823407019233550444836	80	UVM_INFO @ 398485938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	38510946802433273022212324424548083845006980284474265972982835189017045281997	81	UVM_INFO @ 6337774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
	i2c_host_stress_all	115142223900313650725241731047614984830307301813149614702414250376240993544738	117	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @1675824
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	27818462542120692849073389559371153641424177752395235614113573002860879260039	84	UVM_INFO @ 453220200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
	i2c_target_stretch	77782596558877494506901246002671570498523891989855562742964958384973176899352	78	UVM_INFO @ 10018781911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	75581419687199137953656827385722189833105241408972159183311248369130350689264	78	UVM_INFO @ 109339183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	68372836033695574254234843929729309047006090431310950461306501887625426185048	91	UVM_INFO @ 5972558120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	14297154671984357561781180741094379672849200775121171725324023882877577670254	96	UVM_INFO @ 504712076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---