Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.05 %
  • code
  • 86.10 %
  • assert
  • 95.99 %
  • func
  • 94.06 %
  • line
  • 97.63 %
  • branch
  • 95.70 %
  • cond
  • 79.59 %
  • toggle
  • 88.47 %
  • FSM
  • 69.09 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.030s 46.384us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.970s 126.164us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.870s 18.899us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.060s 133.324us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 77.688us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.360s 30.608us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.870s 18.899us 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 77.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.540s 288.558us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.900s 735.677us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.110s 101.282us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.950s 46.518us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.910s 2596.833us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_prog_failure 1.950s 46.518us 1 1 100.00
lc_ctrl_errors 8.910s 2596.833us 1 1 100.00
lc_ctrl_security_escalation 4.850s 567.572us 1 1 100.00
lc_ctrl_jtag_state_failure 38.590s 3653.123us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.540s 864.675us 1 1 100.00
lc_ctrl_jtag_errors 16.640s 7648.828us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 12.690s 2833.232us 1 1 100.00
lc_ctrl_jtag_state_post_trans 23.810s 4842.513us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.540s 864.675us 1 1 100.00
lc_ctrl_jtag_errors 16.640s 7648.828us 1 1 100.00
lc_ctrl_jtag_access 3.670s 420.717us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.060s 2862.750us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.950s 48.812us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.040s 88.460us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.550s 529.881us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.360s 2775.715us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.700s 47.066us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.620s 1746.451us 1 1 100.00
lc_ctrl_jtag_alert_test 0.900s 62.869us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.470s 2016.003us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.730s 135.546us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 154.930s 16651.276us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.160s 103.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.740s 36.175us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.740s 36.175us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.970s 126.164us 1 1 100.00
lc_ctrl_csr_rw 0.870s 18.899us 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 77.688us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.340s 22.302us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.970s 126.164us 1 1 100.00
lc_ctrl_csr_rw 0.870s 18.899us 1 1 100.00
lc_ctrl_csr_aliasing 1.460s 77.688us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.340s 22.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
lc_ctrl_tl_intg_err 2.860s 223.917us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.860s 223.917us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.900s 735.677us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.070s 622.288us 1 1 100.00
lc_ctrl_sec_cm 5.500s 229.769us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.850s 567.572us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.540s 288.558us 1 1 100.00
lc_ctrl_jtag_state_post_trans 23.810s 4842.513us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.880s 314.923us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.880s 314.923us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.120s 596.607us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.280s 810.628us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.280s 810.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 27.150s 10007.710us 1 1 100.00