Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.12 %
  • code
  • 84.93 %
  • assert
  • 95.99 %
  • func
  • 92.45 %
  • line
  • 97.87 %
  • branch
  • 96.43 %
  • cond
  • 80.35 %
  • toggle
  • 88.18 %
  • FSM
  • 61.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.590s 44.172us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.050s 81.658us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.850s 44.907us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.100s 200.325us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 27.857us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.640s 109.194us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.850s 44.907us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 27.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.260s 207.686us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.520s 208.370us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 14.301us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.650s 17.460us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 11.240s 770.351us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_prog_failure 1.650s 17.460us 1 1 100.00
lc_ctrl_errors 11.240s 770.351us 1 1 100.00
lc_ctrl_security_escalation 7.020s 302.881us 1 1 100.00
lc_ctrl_jtag_state_failure 60.350s 35258.536us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.040s 571.416us 1 1 100.00
lc_ctrl_jtag_errors 34.510s 1852.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.430s 324.885us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.460s 2485.269us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.040s 571.416us 1 1 100.00
lc_ctrl_jtag_errors 34.510s 1852.000us 1 1 100.00
lc_ctrl_jtag_access 7.320s 5418.665us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.380s 4026.898us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.790s 318.621us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.290s 1884.776us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.130s 388.477us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.060s 1958.070us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.100s 388.452us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.560s 147.935us 1 1 100.00
lc_ctrl_jtag_alert_test 0.950s 32.017us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 17.320s 1101.423us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.970s 13.171us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 33.220s 14897.519us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 31.086us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.100s 60.920us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.100s 60.920us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.050s 81.658us 1 1 100.00
lc_ctrl_csr_rw 0.850s 44.907us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 27.857us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.490s 58.090us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.050s 81.658us 1 1 100.00
lc_ctrl_csr_rw 0.850s 44.907us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 27.857us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.490s 58.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
lc_ctrl_tl_intg_err 1.480s 66.504us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.480s 66.504us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.520s 208.370us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.220s 1227.897us 1 1 100.00
lc_ctrl_sec_cm 7.550s 957.971us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.020s 302.881us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.260s 207.686us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.460s 2485.269us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.370s 935.176us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.370s 935.176us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.830s 2044.823us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.190s 691.399us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.190s 691.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 24.280s 5404.004us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 13828709790910256371345575003000660436214190598838860729843615499687346042387 9103
UVM_INFO @ 5404004331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---