Simulation Results: mbx

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.39 %
  • code
  • 87.97 %
  • assert
  • 96.96 %
  • func
  • 77.24 %
  • block
  • 94.53 %
  • line
  • 94.44 %
  • branch
  • 85.23 %
  • toggle
  • 84.23 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 47.000s 3735.123us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 24.157us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 14.833us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 818.534us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 23.224us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 2.998us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 14.833us 1 1 100.00
mbx_csr_aliasing 2.000s 23.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 4.000s 873.899us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 1.000s 1.213us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 2.000s 38.021us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 8.000s 1477.039us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 14.130us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 47.380us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 1.371us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 1.371us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 24.157us 1 1 100.00
mbx_csr_rw 1.000s 14.833us 1 1 100.00
mbx_csr_aliasing 2.000s 23.224us 1 1 100.00
mbx_same_csr_outstanding 2.000s 85.144us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 24.157us 1 1 100.00
mbx_csr_rw 1.000s 14.833us 1 1 100.00
mbx_csr_aliasing 2.000s 23.224us 1 1 100.00
mbx_same_csr_outstanding 2.000s 85.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 507.431us 1 1 100.00
mbx_sec_cm 1.000s 12.272us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress 87941770852166955241107706577474283820727654810655284718437746435501709582743 259
UVM_INFO @ 873899219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress_zero_delays 9285411099419602709390903485629224737133275739343683220620108519554571566666 89
UVM_INFO @ 1212950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_imbx_oob 60403219467123752240324595390416613629767734317855631269589009678913039307590 89
UVM_INFO @ 38020788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 63805427986790070520916703657272325183711680428212568359956225388367009324059 85
TL item was: req: (cip_tl_seq_item@15368) { a_addr: 'h72411554 a_data: 'hd22bd882 a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'h14 a_opcode: 'h1 a_user: 'h27da3 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1370810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 56488682438637021021760617932361048695861973950652607402371107800688666921804 86
TL item was: req: (cip_tl_seq_item@18721) { a_addr: 'h13c5c0f4 a_data: 'hf00da5c5 a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'h5f a_opcode: 'h1 a_user: 'h26936 d_param: 'h0 d_source: 'h5f d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2997718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---