Simulation Results: otp_ctrl

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.60 %
  • code
  • 69.42 %
  • assert
  • 90.53 %
  • func
  • 48.84 %
  • line
  • 87.38 %
  • branch
  • 82.39 %
  • cond
  • 84.89 %
  • toggle
  • 54.30 %
  • FSM
  • 38.14 %
Validation stages
V1
100.00%
V2
60.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.680s 183.377us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.560s 1062.844us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.040s 86.236us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.220s 202.481us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.510s 321.794us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.620s 1374.011us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.400s 160.144us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.220s 202.481us 1 1 100.00
otp_ctrl_csr_aliasing 5.620s 1374.011us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.900s 557.936us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.360s 101.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 126.470s 38452.074us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.910s 134.770us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 7.160s 568.353us 0 1 0.00
otp_ctrl_check_fail 2.840s 148.035us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.720s 477.245us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 3.750s 197.551us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 4.440s 382.670us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 1.840s 40.811us 0 1 0.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 17.630s 401.075us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.620s 232.689us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 8.420s 4058.422us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 43.370s 1895.018us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.450s 46.916us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.890s 77.147us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 6.740s 2819.739us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 6.740s 2819.739us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.040s 86.236us 1 1 100.00
otp_ctrl_csr_rw 2.220s 202.481us 1 1 100.00
otp_ctrl_csr_aliasing 5.620s 1374.011us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.730s 1982.212us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.040s 86.236us 1 1 100.00
otp_ctrl_csr_rw 2.220s 202.481us 1 1 100.00
otp_ctrl_csr_aliasing 5.620s 1374.011us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.730s 1982.212us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
otp_ctrl_tl_intg_err 12.210s 2176.088us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.210s 2176.088us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.560s 1062.844us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.560s 1062.844us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
otp_ctrl_macro_errs 2.620s 232.689us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
otp_ctrl_macro_errs 2.620s 232.689us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 53.870s 21689.901us 1 1 100.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.910s 134.770us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.840s 148.035us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 3.750s 197.551us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 3.750s 197.551us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 3.750s 197.551us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 3.750s 197.551us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 3.750s 197.551us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.560s 1062.844us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 3.750s 197.551us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.560s 1062.844us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 166.140s 15074.489us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.720s 477.245us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.560s 1062.844us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.560s 1062.844us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.620s 232.689us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 58.120s 21875.124us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 4.620s 156.420us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_partition_walk 20698163335223570470990985161554872712321560222570021785174215560767299455126 165463
UVM_INFO @ 38452073620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 53031640608617176168750875997824488984245288721524036125729186854396795958861 89
UVM_INFO @ 21875123550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 22991551318949879288972764207337900083717833401768265634546423551279797990677 8321
UVM_INFO @ 568352792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 17789489185215120930060170525907406009137655274005006464554657405220857455442 776
UVM_INFO @ 40811338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 84842800648943028807072351634260369891986543518711316159727667548038231644416 2406
UVM_INFO @ 197551176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 51231493344448460326969432890602255522364796042029552669652575570547787723579 4265
UVM_INFO @ 4058422359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 91865000511292686060813065181274964792768939587328036739878229266473091723429 1992
UVM_INFO @ 148034994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 10300531162341676632918655734027603232676262085389419546043361519968215263420 2488
UVM_INFO @ 232688895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 76072692067993066280273533094022288769847492693899880262288078215842077885565 1895
UVM_INFO @ 156420326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_stress_all 44441594443976274388943098511512160620555994690373409034989977323782263173684 57925
UVM_INFO @ 1895017869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 79313827982766327633033816358712830761694072705458208764603994433758228375039 2040
UVM_INFO @ 15074488687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---