Simulation Results: rom_ctrl/32kb

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.88 %
  • code
  • 97.90 %
  • assert
  • 96.80 %
  • func
  • 95.94 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 99.90 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.700s 481.710us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.330s 275.463us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.380s 206.633us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.390s 223.191us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.170s 347.703us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.890s 186.819us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.380s 206.633us 1 1 100.00
rom_ctrl_csr_aliasing 3.170s 347.703us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.350s 765.850us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.090s 530.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.760s 183.953us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.650s 1134.618us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.970s 1925.204us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.850s 292.970us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.650s 562.278us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.650s 562.278us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.330s 275.463us 1 1 100.00
rom_ctrl_csr_rw 3.380s 206.633us 1 1 100.00
rom_ctrl_csr_aliasing 3.170s 347.703us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.340s 252.935us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.330s 275.463us 1 1 100.00
rom_ctrl_csr_rw 3.380s 206.633us 1 1 100.00
rom_ctrl_csr_aliasing 3.170s 347.703us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.340s 252.935us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.430s 1573.689us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 193.970s 1635.754us 1 1 100.00
rom_ctrl_tl_intg_err 23.920s 269.440us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 193.970s 1635.754us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 193.970s 1635.754us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.970s 1635.754us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 193.970s 1635.754us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.700s 481.710us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.700s 481.710us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.700s 481.710us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.920s 269.440us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
rom_ctrl_kmac_err_chk 5.970s 1925.204us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 56.860s 3758.009us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.430s 1573.689us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.970s 1635.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 109.120s 4372.852us 1 1 100.00