Simulation Results: rom_ctrl/64kb

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.18 %
  • code
  • 99.42 %
  • assert
  • 96.66 %
  • func
  • 95.47 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 97.92 %
  • toggle
  • 99.97 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.850s 747.940us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.700s 295.301us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.850s 383.732us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.740s 218.750us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.950s 556.314us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.940s 312.930us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.850s 383.732us 1 1 100.00
rom_ctrl_csr_aliasing 5.950s 556.314us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.130s 372.637us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.390s 209.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.290s 1135.201us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.230s 2191.209us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.710s 2107.868us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.350s 295.301us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 11.070s 295.170us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 11.070s 295.170us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.700s 295.301us 1 1 100.00
rom_ctrl_csr_rw 5.850s 383.732us 1 1 100.00
rom_ctrl_csr_aliasing 5.950s 556.314us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.580s 4728.025us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.700s 295.301us 1 1 100.00
rom_ctrl_csr_rw 5.850s 383.732us 1 1 100.00
rom_ctrl_csr_aliasing 5.950s 556.314us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.580s 4728.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.700s 9559.009us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 229.110s 406.136us 1 1 100.00
rom_ctrl_tl_intg_err 52.470s 385.657us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 229.110s 406.136us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 229.110s 406.136us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 229.110s 406.136us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 229.110s 406.136us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.850s 747.940us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.850s 747.940us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.850s 747.940us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 52.470s 385.657us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
rom_ctrl_kmac_err_chk 14.710s 2107.868us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 181.440s 11480.933us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.700s 9559.009us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 229.110s 406.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 19.260s 737.247us 1 1 100.00