Simulation Results: rstmgr

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.73 %
  • code
  • 99.26 %
  • assert
  • 97.25 %
  • func
  • 93.67 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.52 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.160s 67.941us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.260s 63.727us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.100s 36.481us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.030s 51.260us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.990s 37.940us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.260s 67.860us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.100s 36.481us 1 1 100.00
rstmgr_csr_aliasing 0.990s 37.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.440s 131.342us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.920s 36.838us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.350s 91.692us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.800s 763.439us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.800s 763.439us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.800s 763.439us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.800s 763.439us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.910s 2049.152us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.110s 46.744us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.440s 42.293us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.440s 42.293us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.260s 63.727us 1 1 100.00
rstmgr_csr_rw 1.100s 36.481us 1 1 100.00
rstmgr_csr_aliasing 0.990s 37.940us 1 1 100.00
rstmgr_same_csr_outstanding 1.000s 40.010us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.260s 63.727us 1 1 100.00
rstmgr_csr_rw 1.100s 36.481us 1 1 100.00
rstmgr_csr_aliasing 0.990s 37.940us 1 1 100.00
rstmgr_same_csr_outstanding 1.000s 40.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 17.500s 3387.029us 1 1 100.00
rstmgr_tl_intg_err 4.290s 633.702us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 17.500s 3387.029us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 17.500s 3387.029us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.290s 633.702us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.210s 64.136us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.990s 460.925us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.090s 291.703us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 17.500s 3387.029us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.100s 36.481us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.100s 36.481us 1 1 100.00