Simulation Results

Simulation Results: rv_dm/use_dmi_interface

27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.47 %

code
73.57 %

assert
96.09 %

func
47.76 %

line
90.22 %

branch
75.00 %

cond
76.32 %

toggle
70.04 %

FSM
56.25 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	3.720s	2792.881us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	1.450s	182.669us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	0.720s	97.418us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	7.320s	5694.556us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.160s	496.552us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	6.760s	8311.381us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	7.450s	3437.381us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	21.780s	18756.873us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	72.770s	91558.351us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	2.630s	1468.052us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	0.890s	321.150us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	1.420s	613.425us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.840s	150.380us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	0.860s	136.502us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	4.200s	1875.990us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	1.020s	316.843us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.110s	406.811us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	2.630s	1468.052us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	1.320s	292.583us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	1.160s	841.850us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	1.420s	613.425us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.760s	84.055us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	1.780s	87.598us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.350s	140.755us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	57.730s	30389.801us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	22.730s	4648.521us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	2.760s	104.115us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	22.730s	4648.521us	1	1	100.00
	rv_dm_csr_rw	1.350s	140.755us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.720s	27.899us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.860s	163.769us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	3.720s	2792.881us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	1.040s	158.340us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.820s	153.920us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	1.170s	624.273us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	1.600s	488.046us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	212.740s	300000.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	139.670s	300000.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	257.500s	300000.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	528.270s	300000.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.890s	84.585us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	4.180s	3486.652us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	0.820s	143.324us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.790s	200.639us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	14.930s	14862.240us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	14.960s	3991.710us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.760s	65.720us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	1.500s	1479.191us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.770s	121.593us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	2.550s	208.330us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	2.550s	208.330us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	22.730s	4648.521us	1	1	100.00
	rv_dm_csr_hw_reset	1.780s	87.598us	1	1	100.00
	rv_dm_csr_rw	1.350s	140.755us	1	1	100.00
	rv_dm_same_csr_outstanding	4.790s	352.770us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	22.730s	4648.521us	1	1	100.00
	rv_dm_csr_hw_reset	1.780s	87.598us	1	1	100.00
	rv_dm_csr_rw	1.350s	140.755us	1	1	100.00
	rv_dm_same_csr_outstanding	4.790s	352.770us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	1.230s	754.670us	1	1	100.00
	rv_dm_tl_intg_err	11.920s	6979.912us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	11.920s	6979.912us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	4.180s	3486.652us	1	1	100.00
	rv_dm_debug_disabled	1.160s	62.134us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	4.180s	3486.652us	1	1	100.00
	rv_dm_debug_disabled	1.160s	62.134us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	3.720s	2792.881us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	1.120s	267.986us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.760s	98.529us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.760s	98.529us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	1.120s	267.986us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	1.790s	287.824us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	516.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	80908312338701764140808892584813200797963195825353856640463970946550612825363	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	73171201171457802957129576320665966570216411016543928415447556711137418473445	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	22567436845728992984783988152995109874413701487546157071635226438014739391161	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	6111888849972403729819360126820862844084159474846635728621329039705490486348	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	77447109500456663323288110319255012224877338814131228770673962403315662056758	77	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	61608421346909516237886365213322367498525393035071298329233473960308994821836	77	UVM_INFO @ 150379581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	68284958777930867289807752014860139762518210011365869825887512143258256713448	81	UVM_INFO @ 287824001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	28239603856222632810711944170730479752709677718266504279930050841344543729294	77	UVM_INFO @ 200638803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	98778480208335777406137309849068425308845681459902617037824901783049815321664	77	UVM_INFO @ 84584856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	109698112374823219292740026713501099501611027694564114664382311087596192097841	84	UVM_INFO @ 1479191015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---