Simulation Results: rv_timer

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.44 %
  • code
  • 99.84 %
  • assert
  • 96.82 %
  • func
  • 92.65 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.750s 79.859us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.750s 52.085us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.610s 14.382us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.350s 194.579us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.670s 19.842us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 22.541us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.610s 14.382us 1 1 100.00
rv_timer_csr_aliasing 0.670s 19.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.870s 138.810us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.920s 692.900us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 61.400s 51501.103us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 61.400s 51501.103us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.470s 3848.239us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.580s 48.562us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.600s 14.673us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.040s 65.088us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.040s 65.088us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.750s 52.085us 1 1 100.00
rv_timer_csr_rw 0.610s 14.382us 1 1 100.00
rv_timer_csr_aliasing 0.670s 19.842us 1 1 100.00
rv_timer_same_csr_outstanding 0.810s 38.825us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.750s 52.085us 1 1 100.00
rv_timer_csr_rw 0.610s 14.382us 1 1 100.00
rv_timer_csr_aliasing 0.670s 19.842us 1 1 100.00
rv_timer_same_csr_outstanding 0.810s 38.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.830s 70.085us 1 1 100.00
rv_timer_tl_intg_err 1.130s 321.690us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.130s 321.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.610s 237.580us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 70.090us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 11.730s 7922.863us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 115167392166830310982001151659457910452077148199161879112393524605225893892642 75
UVM_INFO @ 237580081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 89273617067766551615067662471087708238937658722198156203061281138591116564190 76
UVM_INFO @ 138810237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 101856001770488368458898343747668546527013602019018106381552186483958583833762 75
UVM_INFO @ 70090218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---