Simulation Results: spi_device/1r1w

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.28 %
  • code
  • 93.24 %
  • assert
  • 87.53 %
  • func
  • 72.07 %
  • line
  • 99.07 %
  • branch
  • 98.30 %
  • cond
  • 95.91 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 122.180s 81644.209us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.040s 53.787us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.870s 68.304us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 22.430s 1163.313us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.140s 613.411us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.830s 549.054us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.870s 68.304us 1 1 100.00
spi_device_csr_aliasing 11.140s 613.411us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.860s 28.677us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.740s 25.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.800s 20.255us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.730s 7.584us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.800s 3.689us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.190s 77.228us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.190s 77.228us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.990s 22.488us 1 1 100.00
spi_device_tpm_sts_read 0.850s 62.918us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 5.010s 11888.530us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.720s 452.458us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.140s 11816.905us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.140s 11816.905us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 18.220s 37610.331us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 18.220s 37610.331us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 18.220s 37610.331us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 18.220s 37610.331us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 18.220s 37610.331us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 7.690s 10401.341us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 14.260s 17976.411us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 14.260s 17976.411us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 14.260s 17976.411us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.690s 59.873us 1 1 100.00
spi_device_read_buffer_direct 10.360s 2000.982us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 14.260s 17976.411us 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 43.460s 29641.800us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.280s 1469.453us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.280s 1469.453us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 122.180s 81644.209us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 46.120s 17804.418us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 223.820s 50510.006us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.760s 188.605us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.940s 20.321us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.280s 619.554us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.280s 619.554us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.040s 53.787us 1 1 100.00
spi_device_csr_rw 1.870s 68.304us 1 1 100.00
spi_device_csr_aliasing 11.140s 613.411us 1 1 100.00
spi_device_same_csr_outstanding 1.520s 102.583us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.040s 53.787us 1 1 100.00
spi_device_csr_rw 1.870s 68.304us 1 1 100.00
spi_device_csr_aliasing 11.140s 613.411us 1 1 100.00
spi_device_same_csr_outstanding 1.520s 102.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.140s 116.638us 1 1 100.00
spi_device_tl_intg_err 10.780s 1147.282us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.780s 1147.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
spi_device_flash_mode_ignore_cmds 1087.570s 1500000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 45040493577391965091456256460636186913096570705397554101535283086005038761692 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4541914 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4541914 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[900])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 45257044462747354652119060627419378642709644404080583857557476365070154113590 76
UVM_ERROR @ 1283396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2f7bc0 [1011110111101111000000] vs 0x0 [0])
UVM_ERROR @ 1306396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa57887 [101001010111100010000111] vs 0x0 [0])
UVM_ERROR @ 1307396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x223bbd [1000100011101110111101] vs 0x0 [0])
UVM_ERROR @ 1367396 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbbf658 [101110111111011001011000] vs 0x0 [0])
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_device_flash_mode_ignore_cmds 44967563246242507627505026736779013346908598051059721872964847896232301877375 114
UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---