Simulation Results: sram_ctrl/main

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.76 %
  • code
  • 96.81 %
  • assert
  • 96.46 %
  • func
  • 94.00 %
  • block
  • 96.08 %
  • line
  • 96.81 %
  • branch
  • 94.33 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 713.688us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 76.643us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 42.702us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 75.868us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 51.713us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 395.362us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 42.702us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 51.713us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 225.000s 86135.803us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 61.000s 43638.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 2464.968us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 154.000s 20701.068us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 114.000s 6157.136us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 56.000s 11660.645us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 6217.901us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 2583.681us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 2018.137us 1 1 100.00
sram_ctrl_partial_access_b2b 151.000s 80562.526us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 10.000s 8313.125us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 699.385us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 2791.010us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 445.855us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1593.029us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 58.000s 30038.316us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 36.469us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 280.592us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 280.592us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 76.643us 1 1 100.00
sram_ctrl_csr_rw 1.000s 42.702us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 51.713us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 162.197us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 76.643us 1 1 100.00
sram_ctrl_csr_rw 1.000s 42.702us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 51.713us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 162.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 7282.506us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1569.056us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 160.895us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1569.056us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 160.895us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 445.855us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 445.855us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 42.702us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2583.681us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2583.681us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2583.681us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 6217.901us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 668.974us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 7282.506us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2758.556us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 713.688us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 713.688us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 2583.681us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1569.056us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 6217.901us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1569.056us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1569.056us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 713.688us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1569.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 52.000s 3144.918us 1 1 100.00