Simulation Results: uart

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.20 %
  • code
  • 94.86 %
  • assert
  • 97.12 %
  • func
  • 48.61 %
  • line
  • 98.86 %
  • branch
  • 96.27 %
  • cond
  • 92.77 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.740s 142.330us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 58.189us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 18.893us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.870s 698.036us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.700s 23.024us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.710s 368.753us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 18.893us 1 1 100.00
uart_csr_aliasing 0.700s 23.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 29.200s 26471.869us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.740s 142.330us 1 1 100.00
uart_tx_rx 29.200s 26471.869us 1 1 100.00
parity_error 2 2 100.00
uart_intr 6.700s 36714.717us 1 1 100.00
uart_rx_parity_err 72.780s 62305.011us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 29.200s 26471.869us 1 1 100.00
uart_intr 6.700s 36714.717us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 34.420s 107127.316us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 68.400s 61974.190us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 19.920s 66016.676us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 6.700s 36714.717us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 6.700s 36714.717us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 6.700s 36714.717us 1 1 100.00
perf 1 1 100.00
uart_perf 37.210s 13246.127us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.530s 4343.694us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.530s 4343.694us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 10.380s 26156.465us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.060s 3936.805us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.200s 1380.511us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.840s 3465.359us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 125.520s 66549.408us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 0.640s 20.495us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.570s 43.195us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.600s 32.498us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.890s 44.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.890s 44.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 58.189us 1 1 100.00
uart_csr_rw 0.580s 18.893us 1 1 100.00
uart_csr_aliasing 0.700s 23.024us 1 1 100.00
uart_same_csr_outstanding 0.760s 20.363us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 58.189us 1 1 100.00
uart_csr_rw 0.580s 18.893us 1 1 100.00
uart_csr_aliasing 0.700s 23.024us 1 1 100.00
uart_same_csr_outstanding 0.760s 20.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.160s 74.187us 1 1 100.00
uart_tl_intg_err 1.100s 379.281us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.100s 379.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 18.020s 5362.874us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 21718640371661340087769234845471632401603994870571794172680701220084086995696 78
UVM_ERROR @ 6165807748 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6166014646 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6262773944 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6262773944 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_stress_all 49074285054561495730057938446164365734681877410578447172189452779019828849635 75
UVM_ERROR @ 9240285 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9454569 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9689261 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9903545 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0