Simulation Results: aes/masked

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.52 %
  • code
  • 94.61 %
  • assert
  • 98.43 %
  • func
  • 66.51 %
  • block
  • 95.74 %
  • line
  • 97.40 %
  • branch
  • 89.42 %
  • toggle
  • 98.05 %
  • FSM
  • 93.55 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 158.342us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 217.800us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 58.817us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 59.210us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 1568.933us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 490.683us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 137.971us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 59.210us 1 1 100.00
aes_csr_aliasing 3.000s 490.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 217.800us 1 1 100.00
aes_config_error 2.000s 66.725us 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 217.800us 1 1 100.00
aes_config_error 2.000s 66.725us 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 360.596us 1 1 100.00
aes_b2b 13.000s 229.067us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 217.800us 1 1 100.00
aes_config_error 2.000s 66.725us 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
aes_alert_reset 29.000s 10025.953us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 146.147us 1 1 100.00
aes_config_error 2.000s 66.725us 1 1 100.00
aes_alert_reset 29.000s 10025.953us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 76.199us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 1002.692us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 199.242us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 29.000s 10025.953us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 360.596us 1 1 100.00
aes_sideload 6.000s 528.474us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 151.955us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 5.000s 116.948us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 86.819us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 80.432us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 105.726us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 105.726us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.817us 1 1 100.00
aes_csr_rw 2.000s 59.210us 1 1 100.00
aes_csr_aliasing 3.000s 490.683us 1 1 100.00
aes_same_csr_outstanding 2.000s 171.119us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 58.817us 1 1 100.00
aes_csr_rw 2.000s 59.210us 1 1 100.00
aes_csr_aliasing 3.000s 490.683us 1 1 100.00
aes_same_csr_outstanding 2.000s 171.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 780.795us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_cipher_fi 2.000s 64.006us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 332.382us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 332.382us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 332.382us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 332.382us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 722.627us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1879.915us 1 1 100.00
aes_tl_intg_err 2.000s 197.180us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 197.180us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 29.000s 10025.953us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 332.382us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 332.382us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 217.800us 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
aes_alert_reset 29.000s 10025.953us 0 1 0.00
aes_core_fi 2.000s 108.957us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 86.819us 1 1 100.00
aes_config_error 2.000s 66.725us 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
aes_core_fi 2.000s 108.957us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 332.382us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 87.569us 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 360.596us 1 1 100.00
aes_sideload 6.000s 528.474us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 87.569us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 87.569us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 87.569us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 87.569us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 87.569us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 360.596us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 21.000s 10027.378us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_cipher_fi 2.000s 64.006us 1 1 100.00
aes_ctr_fi 2.000s 60.983us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 21.000s 10027.378us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_cipher_fi 2.000s 64.006us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 64.006us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 21.000s 10027.378us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_ctr_fi 2.000s 60.983us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 21.000s 10027.378us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_cipher_fi 2.000s 64.006us 1 1 100.00
aes_ctr_fi 2.000s 60.983us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 29.000s 10025.953us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_cipher_fi 2.000s 64.006us 1 1 100.00
aes_ctr_fi 2.000s 60.983us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_cipher_fi 2.000s 64.006us 1 1 100.00
aes_ctr_fi 2.000s 60.983us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_ctr_fi 2.000s 60.983us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 21.000s 10027.378us 0 1 0.00
aes_ghash_fi 2.000s 64.652us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 21.000s 10027.378us 0 1 0.00
aes_control_fi 3.000s 77.876us 1 1 100.00
aes_cipher_fi 2.000s 64.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 18.000s 2063.573us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 112936212103598995711131562025422663487803259477573001888523928679094307485971 874
UVM_INFO @ 10025952512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 103218698423592699647419734425992951260160766619769935724794797816294547353242 2853
UVM_INFO @ 10027377930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 41820115923205314612257279124789233259817143084091304726741145936713163056913 416
UVM_INFO @ 2063573433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---