Simulation Results: aes/unmasked

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.15 %
  • code
  • 90.89 %
  • assert
  • 97.57 %
  • func
  • 66.98 %
  • block
  • 90.97 %
  • line
  • 93.37 %
  • branch
  • 83.54 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 67.410us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 93.745us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 162.122us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 78.961us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 510.447us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 1513.211us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 167.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 78.961us 1 1 100.00
aes_csr_aliasing 3.000s 1513.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 93.745us 1 1 100.00
aes_config_error 2.000s 106.354us 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 93.745us 1 1 100.00
aes_config_error 2.000s 106.354us 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 204.519us 1 1 100.00
aes_b2b 6.000s 356.299us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 93.745us 1 1 100.00
aes_config_error 2.000s 106.354us 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
aes_alert_reset 28.000s 10013.129us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 1.000s 78.922us 1 1 100.00
aes_config_error 2.000s 106.354us 1 1 100.00
aes_alert_reset 28.000s 10013.129us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 77.587us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 307.449us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 352.063us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 28.000s 10013.129us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 204.519us 1 1 100.00
aes_sideload 3.000s 62.968us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 449.063us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 8.000s 10143.901us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 62.346us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 81.756us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 170.551us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 170.551us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 162.122us 1 1 100.00
aes_csr_rw 1.000s 78.961us 1 1 100.00
aes_csr_aliasing 3.000s 1513.211us 1 1 100.00
aes_same_csr_outstanding 3.000s 85.177us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 162.122us 1 1 100.00
aes_csr_rw 1.000s 78.961us 1 1 100.00
aes_csr_aliasing 3.000s 1513.211us 1 1 100.00
aes_same_csr_outstanding 3.000s 85.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 265.122us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_cipher_fi 2.000s 48.531us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 101.497us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 101.497us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 101.497us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 101.497us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 203.825us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 3271.569us 1 1 100.00
aes_tl_intg_err 2.000s 89.477us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 89.477us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 28.000s 10013.129us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 101.497us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 101.497us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 2.000s 93.745us 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
aes_alert_reset 28.000s 10013.129us 0 1 0.00
aes_core_fi 10.000s 10011.341us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 2.000s 62.346us 1 1 100.00
aes_config_error 2.000s 106.354us 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
aes_core_fi 10.000s 10011.341us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 101.497us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 61.848us 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 204.519us 1 1 100.00
aes_sideload 3.000s 62.968us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 61.848us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 61.848us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 61.848us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 61.848us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 61.848us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 204.519us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 7.000s 10143.706us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_cipher_fi 2.000s 48.531us 1 1 100.00
aes_ctr_fi 2.000s 54.577us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 7.000s 10143.706us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_cipher_fi 2.000s 48.531us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 48.531us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 7.000s 10143.706us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_ctr_fi 2.000s 54.577us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 7.000s 10143.706us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_cipher_fi 2.000s 48.531us 1 1 100.00
aes_ctr_fi 2.000s 54.577us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 28.000s 10013.129us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_cipher_fi 2.000s 48.531us 1 1 100.00
aes_ctr_fi 2.000s 54.577us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_cipher_fi 2.000s 48.531us 1 1 100.00
aes_ctr_fi 2.000s 54.577us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_ctr_fi 2.000s 54.577us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 7.000s 10143.706us 0 1 0.00
aes_ghash_fi 2.000s 94.491us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 7.000s 10143.706us 0 1 0.00
aes_control_fi 2.000s 57.946us 1 1 100.00
aes_cipher_fi 2.000s 48.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 11.000s 1713.685us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 77751009195379979645494547824155623345225484957788232351012875776553533171536 2287
UVM_INFO @ 10013128806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 44194349582572847333889676718880076600625760997359298535898631303843229173246 2801
UVM_INFO @ 10143900786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 54346135205549418411337489377435067784605333541876065496220861244335070551800 652
UVM_INFO @ 10143706217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 20852700558792906066829374966899023488855319674759931789622848819472442607539 141
UVM_INFO @ 10011340734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 1388555877689227482892044054221785399882658638363608410873163816300808068551 727
UVM_INFO @ 1713684919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---