Simulation Results: chip

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.90 %
  • code
  • 64.27 %
  • assert
  • 76.61 %
  • func
  • 56.82 %
  • line
  • 67.31 %
  • branch
  • 74.18 %
  • cond
  • 64.97 %
  • toggle
  • 57.76 %
  • FSM
  • 57.14 %
Validation stages
V1
27.27%
V2
31.16%
V2S
100.00%
V3
0.00%
unmapped
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_uart_tx_rx 0 1 0.00
chip_sw_uart_tx_rx 13.785s 0.000us 0 1 0.00
chip_sw_uart_rx_overflow 0 1 0.00
chip_sw_uart_tx_rx 13.785s 0.000us 0 1 0.00
chip_sw_uart_rand_baudrate 0 1 0.00
chip_sw_uart_rand_baudrate 32.212s 0.000us 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 26.916s 0.000us 0 1 0.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 324.040s 296.254us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 324.040s 296.254us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 324.040s 296.254us 1 1 100.00
chip_sw_example_tests 1 4 25.00
chip_sw_example_rom 32.410s 10.360us 0 1 0.00
chip_sw_example_manufacturer 11.913s 0.000us 0 1 0.00
chip_sw_example_concurrency 209.630s 169.992us 1 1 100.00
chip_sw_uart_smoketest_signed 9.504s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
chip_csr_bit_bash 9.220s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 8.880s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 1 0.00
chip_csr_aliasing 8.880s 0.000us 0 1 0.00
xbar_smoke 1 1 100.00
xbar_smoke 24.980s 63.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_spi_device_flash_mode 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 16.738s 0.000us 0 1 0.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 2176.120s 4199.036us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 253.510s 220.456us 0 1 0.00
chip_sw_spi_device_tpm 0 1 0.00
chip_sw_spi_device_tpm 12.140s 0.000us 0 1 0.00
chip_sw_spi_host_tx_rx 0 1 0.00
chip_sw_spi_host_tx_rx 13.481s 0.000us 0 1 0.00
chip_sw_i2c_host_tx_rx 0 1 0.00
chip_sw_i2c_host_tx_rx 20.127s 0.000us 0 1 0.00
chip_sw_i2c_device_tx_rx 0 1 0.00
chip_sw_i2c_device_tx_rx 13.990s 0.000us 0 1 0.00
chip_pin_mux 0 1 0.00
chip_padctrl_attributes 3.020s 0.000us 0 1 0.00
chip_padctrl_attributes 0 1 0.00
chip_padctrl_attributes 3.020s 0.000us 0 1 0.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 28.695s 0.000us 0 1 0.00
chip_sw_sleep_pin_retention 0 1 0.00
chip_sw_sleep_pin_retention 11.326s 0.000us 0 1 0.00
chip_sw_data_integrity 0 1 0.00
chip_sw_data_integrity_escalation 8.847s 0.000us 0 1 0.00
chip_sw_instruction_integrity 0 1 0.00
chip_sw_data_integrity_escalation 8.847s 0.000us 0 1 0.00
chip_jtag_csr_rw 0 1 0.00
chip_jtag_csr_rw 103.160s 117.040us 0 1 0.00
chip_jtag_mem_access 0 1 0.00
chip_jtag_mem_access 95.780s 117.023us 0 1 0.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 328.790s 310.350us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 9.277s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 9.653s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 89.730s 130.696us 0 1 0.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 252.750s 268.453us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 0 1 0.00
chip_sw_aon_timer_irq 430.790s 494.013us 0 1 0.00
chip_sw_aon_timer_wdog_bark_irq 0 1 0.00
chip_sw_aon_timer_irq 430.790s 494.013us 0 1 0.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 408.630s 390.193us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 227.800s 183.917us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 227.800s 183.917us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 371.880s 2309.749us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 190.050s 164.635us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 325.460s 245.229us 1 1 100.00
chip_sw_aes_idle 197.450s 165.644us 1 1 100.00
chip_sw_hmac_enc_idle 218.480s 180.957us 1 1 100.00
chip_sw_kmac_idle 199.990s 164.708us 1 1 100.00
chip_sw_clkmgr_off_trans 0 4 0.00
chip_sw_clkmgr_off_aes_trans 199.950s 185.280us 0 1 0.00
chip_sw_clkmgr_off_hmac_trans 186.720s 185.248us 0 1 0.00
chip_sw_clkmgr_off_kmac_trans 192.610s 185.168us 0 1 0.00
chip_sw_clkmgr_off_otbn_trans 187.820s 185.232us 0 1 0.00
chip_sw_clkmgr_jitter 1 7 14.29
chip_sw_otbn_ecdsa_op_irq_jitter_en 34.970s 10.360us 0 1 0.00
chip_sw_aes_enc_jitter_en 37.420s 10.100us 0 1 0.00
chip_sw_hmac_enc_jitter_en 36.570s 10.260us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 34.060s 10.140us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 38.640s 10.240us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 9.014s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 182.440s 161.090us 1 1 100.00
chip_sw_clkmgr_extended_range 1 8 12.50
chip_sw_clkmgr_jitter_reduced_freq 415.980s 1959.912us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 35.770s 10.280us 0 1 0.00
chip_sw_aes_enc_jitter_en_reduced_freq 35.340s 10.320us 0 1 0.00
chip_sw_hmac_enc_jitter_en_reduced_freq 35.570s 10.100us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 36.550s 10.400us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 36.210s 10.120us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 36.480s 10.120us 0 1 0.00
chip_sw_csrng_edn_concurrency_reduced_freq 35.110s 10.240us 0 1 0.00
chip_sw_clkmgr_deep_sleep_frequency 0 1 0.00
chip_sw_ast_clk_outputs 9.004s 0.000us 0 1 0.00
chip_sw_clkmgr_sleep_frequency 0 1 0.00
chip_sw_clkmgr_sleep_frequency 9.220s 0.000us 0 1 0.00
chip_sw_clkmgr_reset_frequency 0 1 0.00
chip_sw_clkmgr_reset_frequency 10.466s 0.000us 0 1 0.00
chip_sw_clkmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 986.280s 950.746us 0 1 0.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 126.090s 118.472us 0 1 0.00
chip_sw_pwrmgr_sleep_all_reset_reqs 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 227.800s 183.917us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 0 1 0.00
chip_sw_pwrmgr_wdog_reset 9.536s 0.000us 0 1 0.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 126.090s 118.472us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 13.639s 0.000us 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 12.684s 0.000us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 12.712s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 11.228s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 11.952s 0.000us 0 1 0.00
chip_sw_pwrmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 986.280s 950.746us 0 1 0.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 328.790s 310.350us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 390.810s 414.576us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 287.060s 305.597us 1 1 100.00
chip_sw_rstmgr_alert_info 0 1 0.00
chip_sw_rstmgr_alert_info 355.560s 336.545us 0 1 0.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 188.150s 163.290us 1 1 100.00
chip_sw_rstmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 986.280s 950.746us 0 1 0.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 24.386s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 0 1 0.00
chip_sw_alert_handler_escalation 69.283s 0.000us 0 1 0.00
chip_sw_all_escalation_resets 0 1 0.00
chip_sw_all_escalation_resets 986.280s 950.746us 0 1 0.00
chip_sw_alert_handler_entropy 0 1 0.00
chip_sw_alert_handler_entropy 20.008s 0.000us 0 1 0.00
chip_sw_alert_handler_crashdump 0 1 0.00
chip_sw_rstmgr_alert_info 355.560s 336.545us 0 1 0.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 233.480s 205.403us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 60.945s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 83.283s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 74.119s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 86.339s 0.000us 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 87.452s 0.000us 0 1 0.00
chip_sw_lc_ctrl_alert_handler_escalation 0 1 0.00
chip_sw_alert_handler_escalation 69.283s 0.000us 0 1 0.00
chip_sw_lc_ctrl_jtag_access 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 10.469s 0.000us 0 1 0.00
chip_sw_lc_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transitions 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_sw_lc_ctrl_kmac_req 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_sw_lc_ctrl_key_div 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_prod 330.710s 305.620us 0 1 0.00
chip_sw_lc_ctrl_broadcast 0 10 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 9.354s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 13.631s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 10.225s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 9.781s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 329.830s 305.611us 0 1 0.00
chip_sw_rom_ctrl_integrity_check 162.730s 157.528us 0 1 0.00
chip_sw_sram_ctrl_execution_main 9.261s 0.000us 0 1 0.00
chip_prim_tl_access 75.530s 117.432us 0 1 0.00
chip_rv_dm_lc_disabled 89.730s 130.696us 0 1 0.00
chip_sw_aes_enc 1 2 50.00
chip_sw_aes_enc 215.670s 176.093us 1 1 100.00
chip_sw_aes_enc_jitter_en 37.420s 10.100us 0 1 0.00
chip_sw_aes_gcm 1 2 50.00
chip_sw_aes_enc 215.670s 176.093us 1 1 100.00
chip_sw_aes_enc_jitter_en 37.420s 10.100us 0 1 0.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 184.110s 164.940us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 197.450s 165.644us 1 1 100.00
chip_sw_hmac_enc 1 2 50.00
chip_sw_hmac_enc 205.760s 175.740us 1 1 100.00
chip_sw_hmac_enc_jitter_en 36.570s 10.260us 0 1 0.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 218.480s 180.957us 1 1 100.00
chip_sw_kmac_enc 2 3 66.67
chip_sw_kmac_mode_cshake 208.400s 168.409us 1 1 100.00
chip_sw_kmac_mode_kmac 231.980s 191.679us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 38.640s 10.240us 0 1 0.00
chip_sw_kmac_app_keymgr 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 329.830s 305.611us 0 1 0.00
chip_sw_kmac_app_lc 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_sw_kmac_app_rom 0 1 0.00
chip_sw_kmac_app_rom 39.659s 0.000us 0 1 0.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 284.880s 228.879us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 199.990s 164.708us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1536.710s 2224.306us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1536.710s 2224.306us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 11.454s 0.000us 0 1 0.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 230.420s 176.515us 1 1 100.00
chip_sw_edn_entropy_reqs 1 1 100.00
chip_sw_csrng_edn_concurrency 1624.370s 1079.886us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 0 2 0.00
chip_sw_keymgr_dpe_key_derivation 329.830s 305.611us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 34.060s 10.140us 0 1 0.00
chip_sw_otbn_op 1 2 50.00
chip_sw_otbn_ecdsa_op_irq 2683.270s 1502.621us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 34.970s 10.360us 0 1 0.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 325.460s 245.229us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 325.460s 245.229us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 325.460s 245.229us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 369.100s 279.286us 1 1 100.00
chip_sw_rom_access 0 1 0.00
chip_sw_rom_ctrl_integrity_check 162.730s 157.528us 0 1 0.00
chip_sw_rom_ctrl_integrity_check 0 1 0.00
chip_sw_rom_ctrl_integrity_check 162.730s 157.528us 0 1 0.00
chip_sw_sram_scrambled_access 1 2 50.00
chip_sw_sram_ctrl_scrambled_access 419.260s 361.177us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 9.014s 0.000us 0 1 0.00
chip_sw_sram_execution 0 1 0.00
chip_sw_sram_ctrl_execution_main 9.261s 0.000us 0 1 0.00
chip_sw_sram_lc_escalation 0 2 0.00
chip_sw_all_escalation_resets 986.280s 950.746us 0 1 0.00
chip_sw_data_integrity_escalation 8.847s 0.000us 0 1 0.00
chip_otp_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_sw_otp_ctrl_keys 3 4 75.00
chip_sw_otbn_mem_scramble 369.100s 279.286us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 329.830s 305.611us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 419.260s 361.177us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 207.230s 186.477us 1 1 100.00
chip_sw_otp_ctrl_entropy 3 4 75.00
chip_sw_otbn_mem_scramble 369.100s 279.286us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 329.830s 305.611us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 419.260s 361.177us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 207.230s 186.477us 1 1 100.00
chip_sw_otp_ctrl_program 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_sw_otp_ctrl_program_error 0 1 0.00
chip_sw_lc_ctrl_program_error 14.499s 0.000us 0 1 0.00
chip_sw_otp_ctrl_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 10.469s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals 0 6 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 9.354s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 13.631s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 10.225s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 9.781s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 9.163s 0.000us 0 1 0.00
chip_prim_tl_access 75.530s 117.432us 0 1 0.00
chip_sw_otp_prim_tl_access 0 1 0.00
chip_prim_tl_access 75.530s 117.432us 0 1 0.00
chip_sw_otp_ctrl_nvm_cnt 0 1 0.00
chip_sw_otp_ctrl_nvm_cnt 9.035s 0.000us 0 1 0.00
chip_sw_otp_ctrl_sw_parts 0 1 0.00
chip_sw_otp_ctrl_sw_parts 8.928s 0.000us 0 1 0.00
chip_sw_ast_clk_outputs 0 1 0.00
chip_sw_ast_clk_outputs 9.004s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 1 7 14.29
chip_sw_otbn_ecdsa_op_irq_jitter_en 34.970s 10.360us 0 1 0.00
chip_sw_aes_enc_jitter_en 37.420s 10.100us 0 1 0.00
chip_sw_hmac_enc_jitter_en 36.570s 10.260us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 34.060s 10.140us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 38.640s 10.240us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 9.014s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 182.440s 161.090us 1 1 100.00
chip_sw_soc_proxy_external_reset_requests 0 1 0.00
chip_sw_soc_proxy_smoketest 171.170s 156.864us 0 1 0.00
chip_sw_soc_proxy_external_irqs 0 1 0.00
chip_sw_soc_proxy_smoketest 171.170s 156.864us 0 1 0.00
chip_sw_soc_proxy_external_wakeup_requests 0 1 0.00
chip_sw_soc_proxy_external_wakeup 177.400s 157.921us 0 1 0.00
chip_sw_soc_proxy_gpios 1 1 100.00
chip_sw_soc_proxy_gpios 191.580s 180.521us 1 1 100.00
chip_sw_nmi_irq 0 1 0.00
chip_sw_rv_core_ibex_nmi_irq 401.920s 272.176us 0 1 0.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 229.070s 183.659us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 213.710s 184.388us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 207.230s 186.477us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 390.810s 414.576us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 390.810s 414.576us 0 1 0.00
chip_sw_smoketest 14 14 100.00
chip_sw_aes_smoketest 194.720s 176.102us 1 1 100.00
chip_sw_aon_timer_smoketest 220.910s 182.465us 1 1 100.00
chip_sw_clkmgr_smoketest 183.860s 162.108us 1 1 100.00
chip_sw_csrng_smoketest 186.770s 164.432us 1 1 100.00
chip_sw_gpio_smoketest 213.180s 193.105us 1 1 100.00
chip_sw_hmac_smoketest 243.770s 201.417us 1 1 100.00
chip_sw_kmac_smoketest 229.950s 190.405us 1 1 100.00
chip_sw_otbn_smoketest 276.960s 209.963us 1 1 100.00
chip_sw_otp_ctrl_smoketest 186.950s 166.450us 1 1 100.00
chip_sw_rv_plic_smoketest 183.080s 164.295us 1 1 100.00
chip_sw_rv_timer_smoketest 251.450s 268.386us 1 1 100.00
chip_sw_rstmgr_smoketest 188.270s 160.807us 1 1 100.00
chip_sw_sram_ctrl_smoketest 192.190s 164.888us 1 1 100.00
chip_sw_uart_smoketest 195.990s 174.902us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 8.790s 0.000us 0 1 0.00
chip_sw_signed 0 1 0.00
chip_sw_uart_smoketest_signed 9.504s 0.000us 0 1 0.00
chip_sw_boot 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 16.738s 0.000us 0 1 0.00
chip_sw_secure_boot 0 1 0.00
base_rom_e2e_smoke 8.013s 0.000us 0 1 0.00
chip_lc_scrap 0 4 0.00
chip_sw_lc_ctrl_rma_to_scrap 195.290s 167.400us 0 1 0.00
chip_sw_lc_ctrl_raw_to_scrap 149.920s 172.072us 0 1 0.00
chip_sw_lc_ctrl_test_locked0_to_scrap 159.890s 172.456us 0 1 0.00
chip_sw_lc_ctrl_rand_to_scrap 161.300s 170.216us 0 1 0.00
chip_lc_test_locked 0 2 0.00
chip_sw_lc_walkthrough_testunlocks 9.467s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 89.730s 130.696us 0 1 0.00
chip_sw_lc_walkthrough 0 5 0.00
chip_sw_lc_walkthrough_dev 40.399s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 37.518s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 9.119s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_rma 15.709s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 9.467s 0.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 289.860s 373.592us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 387.930s 522.488us 0 1 0.00
rom_volatile_raw_unlock 10.678s 0.000us 0 1 0.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 93.351s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 23.016s 0.000us 0 1 0.00
chip_sw_inject_scramble_seed 0 1 0.00
chip_sw_inject_scramble_seed 73.062s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 105.490s 117.715us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 105.490s 117.715us 0 1 0.00
tl_d_outstanding_access 0 2 0.00
chip_csr_aliasing 8.880s 0.000us 0 1 0.00
chip_same_csr_outstanding 8.920s 0.000us 0 1 0.00
tl_d_partial_access 0 2 0.00
chip_csr_aliasing 8.880s 0.000us 0 1 0.00
chip_same_csr_outstanding 8.920s 0.000us 0 1 0.00
xbar_base_random_sequence 1 1 100.00
xbar_random 84.350s 59.866us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 10.130s 12.836us 1 1 100.00
xbar_smoke_large_delays 334.920s 2683.274us 1 1 100.00
xbar_smoke_slow_rsp 323.950s 1753.877us 1 1 100.00
xbar_random_zero_delays 38.790s 29.443us 1 1 100.00
xbar_random_large_delays 1259.250s 9915.141us 1 1 100.00
xbar_random_slow_rsp 729.020s 3791.660us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 95.800s 154.918us 1 1 100.00
xbar_error_and_unmapped_addr 41.920s 63.062us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 34.680s 28.284us 1 1 100.00
xbar_error_and_unmapped_addr 41.920s 63.062us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 69.520s 144.231us 1 1 100.00
xbar_access_same_device_slow_rsp 2077.620s 11970.732us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 10.160s 11.676us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 289.950s 189.466us 1 1 100.00
xbar_stress_all_with_error 543.060s 440.811us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 709.680s 377.108us 1 1 100.00
xbar_stress_all_with_reset_error 544.750s 359.298us 1 1 100.00
rom_e2e_smoke 0 1 0.00
rom_e2e_smoke 8.247s 0.000us 0 1 0.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 9.091s 0.000us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 14.243s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 100.293s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 9.110s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 9.066s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 8.311s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 8.750s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 94.893s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 9.818s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 8.416s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 9.832s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 11.020s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 114.689s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 14.305s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 10.225s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 13.461s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 10.035s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 149.969s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 25.404s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 23.625s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 27.937s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 34.354s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 86.431s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 15.191s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 14.218s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.382s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 12.779s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 25.375s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 11.299s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 10.105s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 14.989s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 10.700s 0.000us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 53.754s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 17.411s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 15.100s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 14.760s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 12.575s 0.000us 0 1 0.00
rom_e2e_keymgr_init 0 3 0.00
rom_e2e_keymgr_init_rom_ext_meas 15.596s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 15.339s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 25.897s 0.000us 0 1 0.00
rom_e2e_static_critical 0 1 0.00
rom_e2e_static_critical 17.279s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 223.690s 186.391us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 160.840s 131.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 25.722s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 15.312s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 11.072s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 12.262s 0.000us 0 1 0.00
chip_sw_plic_alerts 0 1 0.00
chip_sw_all_escalation_resets 986.280s 950.746us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 12.079s 0.000us 0 1 0.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 205.210s 180.528us 0 1 0.00
chip_sw_coremark 0 1 0.00
chip_sw_coremark 18.925s 0.000us 0 1 0.00
chip_sw_power_max_load 0 1 0.00
chip_sw_power_virus 70.617s 0.000us 0 1 0.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 25.722s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 15.312s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 11.072s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 8.299s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 10.527s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 8.317s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 103.678s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 20 40.00
chip_sw_rstmgr_rst_cnsty_escalation 952.950s 950.693us 0 1 0.00
chip_sw_aes_gcm 250.610s 207.200us 1 1 100.00
chip_sw_entropy_src_kat_test 169.180s 163.432us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 166.510s 161.171us 1 1 100.00
chip_plic_all_irqs_0 476.680s 356.214us 1 1 100.00
chip_plic_all_irqs_10 376.630s 321.358us 1 1 100.00
chip_sw_dma_inline_hashing 241.100s 208.046us 1 1 100.00
chip_sw_dma_abort 255.710s 202.866us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 86.250s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 22.097s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_otbn 8.027s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_sw 12.131s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_otbn 16.635s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_sw 9.122s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_otbn 16.975s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_sw 17.678s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_otbn 9.150s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_sw 8.765s 0.000us 0 1 0.00
chip_sw_entropy_src_smoketest 236.770s 190.148us 1 1 100.00
chip_sw_mbx_smoketest 473.280s 434.757us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
chip_csr_bit_bash 30512746891482384712682524353571928194214157759260453451542482923629943076686 136
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_aliasing 103947299120702916305588205212445815962952540243485343995576847151850331394971 136
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_same_csr_outstanding 77572530479631907903875307857980086241576499763720866832607276815370675987485 136
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode
chip_sw_example_rom 114421320684064648196445795531125593787719251931975398169463430084720808665520 284
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_example_manufacturer 107682418319936418203405030144501272816342537603432078576374863806653195541344 None
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.297s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_data_integrity_escalation 76997599527637193233459232584719155938321335434093789778962242442089862888056 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.267s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sleep_pin_wake 82721014988381523024047111334052032056344323601437617551509365937443250216095 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.720s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sleep_pin_retention 64154727856082796369322985033206919470713669576391677687684119432581990110686 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.216s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx 69099229466733298974807998410760411592623685264577500564259908473428484914449 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.752s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx_bootstrap 54211816553945832552929626392457935466021091474381318352392230637581947722516 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.770s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_inject_scramble_seed 18040773222903819649813082726383539615743455206772119137952555536155525467668 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.867s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_exit_test_unlocked_bootstrap 91405958555709278388662382648665372411314631291682851153353475094029549889908 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 6.547s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_rand_baudrate 55174893894400532999360157879184362951162544686681670954026947326292796947218 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.880s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx_alt_clk_freq 67980066815045391072206718837332972858970420859712390113430594773498699604235 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.378s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_i2c_host_tx_rx 41064131140882546043374423525467137054851530033783558306481526784865227855936 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.240s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_i2c_device_tx_rx 64853800848035128112958980585521056712998813382498118736658765877058834347825 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.211s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_spi_device_tpm 86369683867191394203757977973119036367460963963986695703297101734140398255935 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.353s, Critical Path: 0.09s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_spi_host_tx_rx 38729073445198460479192695441280093168244702520083220816491457196249864893225 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.520s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_otp_hw_cfg 68591133077134501923457599883509304380523384647148268360126705256656026379767 None
---- STDERR ----
Another command (pid=1217277) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=1220267) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_test_unlocked0 105742053658328569019298469696422697073080743560013328051135215065741933415811 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.340s, Critical Path: 0.00s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_dev 95360326650016193004713337005143458600747169743920032647507865564321510397529 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.934s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_prod 49956176719394658089143148582421464899597897628845048473909507204951775204610 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.615s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_rma 54882092501652044194566917478864353202762519018947824868659050211712330779584 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.370s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_vendor_test_csr_access 33388542921156451393985862878543683924206069946534132341816926062353556280561 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.269s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_nvm_cnt 107087970436442409345911579098952943483090833343772508080196277363579105401041 None
---- STDERR ----
Another command (pid=330314) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=530283) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_sw_parts 18819104879211874827159679646650446300992812370755187532004680892407485900491 None
---- STDERR ----
Another command (pid=530283) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=526510) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_transition 21252753711722997405068977702624360330709979638034900660916696533826301157896 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.279s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_dev 83217996878567888480296782760750303686382742657177154249929360893476710561059 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 10.741s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_prod 89757013355857331814881540039344064195421947394299962390944794261659668380216 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.480s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_prodend 68712425503447801274472565817116717405681332723014681161209089420480609973830 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.303s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_rma 10721304994701023712954239417164176974795980783375046192777750932388752832503 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.160s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_testunlocks 53253290842723473864863764257203102748762425353281891884269475327771815900937 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.241s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_main_power_glitch_reset 29240530090881352790096863969617127246773830083343752427111824442185184143156 None
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.298s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_power_glitch_reset 89457130499342532135271413109568659446499028127638703464525190993894551283836 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.505s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 48535787186718470765245950779613278632826942587779554975785163246464029439383 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.849s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_random_sleep_power_glitch_reset 84896810811686384538064872345463029113335206268092188721681947729560486278301 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.233s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_disabled 24696113373796394848760371116768331227801745854549010754397250323004196486352 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.723s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_wdog_reset 22910631514505226975965176190976748211747355622795793261074678412283999041278 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.272s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_test 112124833939510291761775530100983965755877601089058087159973422058679387519032 None
Another command (pid=697726) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_escalation 34188375927130037887342027297497100197683404064572100650019457046162389010005 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.841s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_reverse_ping_in_deep_sleep 56238352830015633390849967572407325668312143768062525361444750868117275858201 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 13.098s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_sleep_mode_alerts 79658037666312307498421271377274416444179121048202131445516378618281041278391 None
Another command (pid=402161) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=402559) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=401713) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_sleep_mode_pings 36947670768862736669403792301493396221168955004906327382830070064385911558665 None
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.931s, Critical Path: 0.05s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
FAILED:
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_clkoff 98701426536012826914194715377153323488921369248241270718970917195475182638147 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.177s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_reset_toggle 77117467673233925660195669169738559494235011827670739918170688066319847290108 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.676s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_entropy 18368862333933127922860388295778933632372070469645135133300097467728264866070 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.273s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_csrng_fuse_en_sw_app_read_test 80911544890560167319451292765555544689991516320439711651520070423771828960857 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.772s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_kmac_app_rom 36485476393453523638377929672557394391637422319475864184491818682603180262908 None
---- STDOUT ----
---- STDERR ----
Another command (pid=1225018) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=1222684) is running. Waiting for it to complete on the server (server_pid=257897)...
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sram_ctrl_scrambled_access_jitter_en 13053412220938752590943771433735364394072472312588318240046092898390516229279 None
---- STDERR ----
Another command (pid=1420054) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sram_ctrl_execution_main 82181431632507763315602231589892849233477162950908114305482879170760540120886 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.227s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_coremark 8038865237767828456447064365219768117475243997374869477032556394270141207929 None
Another command (pid=556822) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_clkmgr_reset_frequency 59864524045746401722099722824939645180736557683880932093939042758106388637458 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.580s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_clkmgr_sleep_frequency 50164074181563282256690382883774360918854040353534945712012483078953893414785 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.264s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_ast_clk_outputs 53249052871972197882350849159458784530714289596119677973943913661774995134431 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.255s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_program_error 90213775998823386163095166700578650435988269173907986003899741386447992051798 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.742s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 84428760744773492959132936885439343691169262282330842510938633556492861473853 None
---- STDERR ----
Another command (pid=1372846) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_access_after_wakeup 58989986134415153918127861511165558314974957949624981393929634977198040723623 None
---- STDERR ----
Another command (pid=1369909) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=1370067) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_access_after_escalation_reset 58195358311842497324570610927425203134153206371024037139472675177993772410045 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.666s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_power_virus 61306756811569733049705403939774095363047213740159976957604954934987211533464 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.515s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
base_rom_e2e_smoke 64724411881011731439352715898609127472756629531718178367211509045583694446341 None
_deploy_software_collateral(args)
~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_smoke 42506901286828291102002765237531603166581973324296706716737807746667784132752 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_shutdown_exception_c 5765400063687591691678902557272486642648023311081035974884150797121657455504 None
Another command (pid=577592) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=586362) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=576364) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_shutdown_output 13159975636181311038835036302050252381769219421694464149935668955830074858886 None
---- STDERR ----
Another command (pid=583540) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=579782) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 96088330949049302639257603641909444495716809159186663346455743632405853875443 None
Another command (pid=489885) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=493784) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=492510) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 113417831132976741833728954929361931945974736506043283343052115173812349197436 None
---- STDERR ----
Another command (pid=535489) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=560822) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 9111272380515353168091642859131228599612294528140079407038306040738284509264 None
---- STDERR ----
Another command (pid=562838) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 40216918016778716932055375074268706803943035892250781739731934014045944162343 None
---- STDERR ----
Another command (pid=567635) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 47946005621249867930091556978955889714633539647440831348601000723562847228664 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 25829693171792229134760244083302768385128602582286087340594964785459643445801 None
Another command (pid=402161) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=401713) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=426996) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 81437349852109182406156032039004610075291092686772297037371178849772849339491 None
Another command (pid=548920) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=548674) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=551540) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 89852491438690778933843226069996143058660679265415343473150621788999841114 None
---- STDERR ----
Another command (pid=548674) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 87216012879743081956068519850823206020769959980675090752917283856684500387 None
Another command (pid=554022) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=551725) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=556822) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 52072990729662725909999402357600432447545381478414775154079362249024617922953 None
Another command (pid=554124) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=535489) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=560822) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 15911233101421736997071634112516891459285373784381518537636055755339142659540 None
Another command (pid=521101) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=505463) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=515689) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 51468765678321298009611270804251467029616926564951038788887999625557290370574 None
Another command (pid=540251) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=535489) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=560822) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 39144785860431859736311503750177756108120292757811410261448568618950134757216 None
---- STDERR ----
Another command (pid=548920) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=548674) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 34444120620873313400442934905978034031774247711786084278007885049517824147365 None
---- STDERR ----
Another command (pid=541298) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=535489) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16953786509975153403440414653852082050415339773299621118544589905129816097461 None
---- STDERR ----
Another command (pid=546416) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=548674) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 113224878135113615815737355515698347979462484831613258381668245779141770042469 None
---- STDERR ----
Another command (pid=422488) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_dev 58098937875083523899257427494484840332461418057736155323896616003093941900517 None
Another command (pid=603934) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=622862) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=576629) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_prod 87311158468825066481958521486716532438600989242310950829982163621625899506472 None
Another command (pid=616928) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=617201) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=611373) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 108823664796190809427598240684865614505951839490006173212483931535082099109182 None
Another command (pid=637596) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=633184) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=635340) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_rma 103675906119405704466127440536459386049532682559173171260152482209415908215123 None
Another command (pid=655625) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=651927) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=659236) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 6947131569501107570374600488824391864291832154128495336005708229967706589652 None
---- STDERR ----
Another command (pid=399622) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=402161) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_dev 29629087867774164624607213807900312119749077797012367831305508426353807966589 None
Another command (pid=616928) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=617201) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=603934) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_prod 2589055324459112557706827370490115966300778435543549071689476505482374820340 None
Another command (pid=617831) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=616928) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=617201) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 105267664489432086041841941866257676034261732206966677232681734864022052722440 None
Another command (pid=622862) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=576629) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=620039) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_rma 65950790545302204587916687242834339982138324879109096862632870955765444855698 None
---- STDERR ----
Another command (pid=611373) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=609079) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 58324737342218731393643080986533074694072217612659604623199710657166174618454 None
---- STDERR ----
Another command (pid=394373) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=396046) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_dev 82168129366660875297789464778132603794677624840183528108320470622832708527355 None
---- STDERR ----
Another command (pid=621645) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=603934) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_prod 103364586698465210553521969881300359921676859406172490610886204687597664395138 None
---- STDERR ----
Another command (pid=618812) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 51965752844552030098152729616673223879878574864990535911706456238420002495339 None
---- STDERR ----
Another command (pid=637596) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_rma 9227369410454720363014010146015477175192269795298385196318107569487703919155 None
Another command (pid=614382) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=603934) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=583042) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 115044827133562492536276963597375015411542015791356874586162567881174268157258 None
Another command (pid=371973) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=377671) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=396046) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 37681573715582263852497559357265279946982389707695385390548862440763129884753 None
Another command (pid=554124) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=535489) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=560822) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 50969998126550853500727723179131761396768552655331491097369445469708306637718 None
Another command (pid=542461) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=551725) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=556822) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 65675160557207390773104417846618514816621925387621920822966556783385510586557 None
Another command (pid=551725) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=556822) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=540251) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 21431469556579393682895692480140793279802559553889013660672672703129036984807 None
Another command (pid=547667) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=546416) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=548674) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_test_unlocked0 98502340603130675689502341474608554514784884934507955514185001231878590861625 None
Another command (pid=616928) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=617201) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=603934) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_dev 98849830959978947280919201432255753076721607150451545310335044962021797967701 None
Another command (pid=586362) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=576364) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=587985) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_rma 19460305778084717096425258173305082700454083945983791062656654717254170174670 None
Another command (pid=583540) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=579782) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=583973) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_test_unlocked0 45325936064142531928020866060284924554254307750977061193348531934712341719104 None
---- STDERR ----
Another command (pid=402982) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_dev 40700447198456432255609990213054331736189074911060348516946580253700085693861 None
Another command (pid=402982) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=510425) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=503655) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_rma 8486418162899020039701395953344832798042807553915273178709451174972096471601 None
---- STDERR ----
Another command (pid=504494) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_static_critical 59831414368600988672902205505898215407009159231190418150350831291835712189497 None
Another command (pid=647209) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=647277) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=664330) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_meas 53257156756296175387711122521653797116388774046298965338259262313172791092035 None
Another command (pid=587985) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=596564) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=592516) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_no_meas 518270655637395863541667377239388535118835335222626251497654463323789033320 None
Another command (pid=588616) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=587985) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=592516) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_invalid_meas 92646671522568111140499510434031389526141428379827211688779857680089860337131 None
Another command (pid=618812) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=614382) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=603934) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 94144103559720800498686334639363050882765377491765474874406636162865077036260 None
Another command (pid=402559) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=401713) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=426996) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 94110798692475733089731702551706066023059952342668358383722530988102504899918 None
Another command (pid=328880) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=371973) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=396171) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_dev_otbn 20610468781069064905726127323906619359342968990965508027389938517110422340209 None
---- STDERR ----
Another command (pid=620039) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_dev_sw 84041085829796556828252797214216231771579956682814370201972857437887799506123 None
Another command (pid=649103) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=648213) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=653959) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_otbn 110633596156882014742744609014621664398581063015169954228565937124786593850155 None
Another command (pid=659236) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=647209) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=647277) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_sw 4617782440107368498146047416782634080957340044109168744116531081948033383182 None
---- STDERR ----
Another command (pid=636882) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_end_otbn 77330866567556644845247815680580418358062204035528878389065046065545490242423 None
Another command (pid=651927) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=659236) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=647209) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_end_sw 81301200505122527980292977173275546369296471413967826565740092502907457895480 None
Another command (pid=647277) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=648514) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=664330) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_rma_otbn 2099824201137868399724285792312787069370866353742201351389970899483244782938 None
---- STDERR ----
Another command (pid=636882) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_rma_sw 92449030063147972830402657937612007479922658798359392085818207132949577502684 None
---- STDERR ----
Another command (pid=636882) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 39250206914446843014012094093377386743539494835729969969539088804507373289551 None
---- STDERR ----
Another command (pid=328880) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=396171) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 45879287765590782143606223097089764595507141255915868785291535943465426890954 None
Another command (pid=521101) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=505463) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=515689) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 50650445212511678678439500994056079746484886739850011452640522392385287706326 None
Another command (pid=487862) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=395855) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=503862) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_smoketest_signed 3451752056338610873097056693370979302436238698022980085100619776752334686037 None
Another command (pid=532660) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=526052) is running. Waiting for it to complete on the server (server_pid=257897)...
Another command (pid=489331) is running. Waiting for it to complete on the server (server_pid=257897)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_keymgr_functest 93286914147002111636280707076497782265429086141374502559458025264095317202534 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.289s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size
chip_sw_all_escalation_resets 25378279430400352070141230701862176636250890663387366909398015104899509522689 352
UVM_INFO @ 950.746000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 32621630609059564246520021802309714799618511146801314186090752134416917419357 348
UVM_INFO @ 950.693000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 6468122883056033827094455502126463954364899011853621882326834631542904427146 332
UVM_INFO @ 220.456000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 61447086450195232983702677298378845199179981281233760128431199239212726110056 328
UVM_ERROR @ 180.528000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 180.528000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
chip_sw_lc_ctrl_rma_to_scrap 36387471516647221527262578092913231345740149351063671290009896003388923364175 325
UVM_ERROR @ 167.400000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 167.400000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_raw_to_scrap 77120202006875827503653538272795233430216037525618843349814964154531238030983 322
UVM_ERROR @ 172.072000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 172.072000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_test_locked0_to_scrap 85797637603401927116725918598876119625655995066361285421653077400102763057436 322
UVM_ERROR @ 172.456000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 172.456000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_rand_to_scrap 112376602627526659687817977574339293361097418913212167614075532218505925872201 322
UVM_ERROR @ 170.216000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 170.216000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_volatile_raw_unlock 109945271775492977268189870180981412064160188660597695263715293613955375284759 325
UVM_ERROR @ 373.592000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 373.592000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 104032299410046354548661242541902882113546346700092996760853540802109357681613 328
UVM_ERROR @ 522.488000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 522.488000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 15238937854506591159294869816829202146957536927964294288317340930468746170076 316
UVM_ERROR @ 118.472000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 118.472000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rom_ctrl_integrity_check 82084890178235839623070820627782142265213287804051491223953847916441411692934 324
UVM_ERROR @ 157.528000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 157.528000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_prim_tl_access 24639472214550465665401079780405726399844274929649656099782686467741905299091 234
UVM_ERROR @ 117.432000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 117.432000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 23269683036577920563914130765966233959536224538675000012872875071702419399396 211
UVM_ERROR @ 130.696000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 130.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size
chip_sw_rstmgr_alert_info 47763532420844794225350656743186696916888171439786099778435180712204814491002 342
UVM_INFO @ 336.545000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!rstreqs[*]) && (reset_cause != HwReq))'
chip_sw_rstmgr_cpu_info 14722744845278197186301965162571330099352765376628595033187598148873042403703 346
UVM_ERROR @ 414.576000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 414.576000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_aes_trans 65475981569056122778982249580132166054976907604759182046504115844566373289613 323
UVM_ERROR @ 185.280000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_hmac_trans 19640057544206890328211399931698002194774316928946953479977644692056546163044 323
UVM_ERROR @ 185.248000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_kmac_trans 43381542326631344648921542480189039250327782485745405732381695069694171935675 323
UVM_ERROR @ 185.168000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.168000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_otbn_trans 34798078143981939484221618322145449005935748307121316974282428919485233391888 323
UVM_ERROR @ 185.232000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.232000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
chip_sw_soc_proxy_smoketest 87330428983282913190447849241049412340031743952319626216575310002596592925071 321
UVM_INFO @ 156.864000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns *
chip_sw_soc_proxy_external_wakeup 12132215362086245247280970072415123917710324535217973939105821396490818900582 319
UVM_INFO @ 157.921000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec
chip_sw_aon_timer_irq 78649084052485278495660350586440765946026686960778325503597716682573670680157 320
UVM_INFO @ 494.013000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds
chip_sw_aon_timer_wdog_bite_reset 66932601497681535570221347229727516840329652011613253481509260063535106538466 321
UVM_INFO @ 183.917000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (dv_utils_pkg.sv:267) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
chip_sw_otbn_ecdsa_op_irq_jitter_en 86458959582020479316015222312535065707937396449642336821356723095097358275535 312
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aes_enc_jitter_en 32111352876760862962286548996925957296559424118668796853482273288050911181875 312
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_enc_jitter_en 111258480580047676575924244638023213599556320517946766362689543137770890015449 312
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_jitter_en 31629436423020715261569103035678579964040579969817336911050692890908236942404 312
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_kmac_mode_kmac_jitter_en 101684419474272845660600623901366025181060792163241174454296852801280862236416 312
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 47485802092354414877092129638765301571084218922944586183604574075703466101907 312
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aes_enc_jitter_en_reduced_freq 92806928499331222621854662801656653505969430245267440321713451163189770058286 312
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_enc_jitter_en_reduced_freq 5090102771353212292145927419100289138008766991470211539467441168975182939327 312
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 107310016424114242925176944059077595901265639164303910464164165199028706906404 312
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 24959662778095388518588025876972865444520035900150870449581487456299228824036 312
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 21971327706761164880582193142684601741640239016905597064269123228038971902672 312
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_edn_concurrency_reduced_freq 101738565105212279253515842359907315887597892022049527411042530593757837395294 312
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired
chip_sw_rv_core_ibex_nmi_irq 17632812053273083339093004450079174685915230511645848532802294306055550129509 322
UVM_INFO @ 272.176000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP
chip_sw_keymgr_dpe_key_derivation 84790828873245243239216289076265702796397569016864080770308249692741979628593 340
UVM_INFO @ 305.611000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_prod 73963433621745777983923794645222407090414792872122164871158839066321554032802 340
UVM_INFO @ 305.620000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)'
chip_tl_errors 53820779232134246836926188970163592254977829232235401171129891531054390102814 232
UVM_ERROR @ 117.715000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
UVM_INFO @ 117.715000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_jtag_csr_rw 29591532361193539899636154876119562385701097573736581827259657948514812151776 5952
TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000 a_data: 'h6de0efc6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h1 a_user: 'h24880 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unmapped address"} .
UVM_INFO @ 117.040000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_jtag_mem_access 106796919640524606967598351409096880396982205363299488271733428165160339146848 5952
TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000 a_data: 'h315b634c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h1 a_user: 'h248b9 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unmapped address"} .
UVM_INFO @ 117.023000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure
chip_padctrl_attributes 41506700658668793583166357887649272806475653981777902469924813957908469034506 281
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
chip_sw_dma_abort 112407155347458093259781446315044351058901217366347778401946565858112547868039 340
UVM_INFO @ 202.866000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---