Simulation Results: clkmgr

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.35 %
  • code
  • 68.45 %
  • assert
  • 89.05 %
  • func
  • 71.54 %
  • line
  • 81.50 %
  • branch
  • 86.18 %
  • cond
  • 77.30 %
  • toggle
  • 97.26 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
53.85%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.940s 26.505us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.480s 124.911us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.650s 5.445us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.770s 5.872us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.860s 7.299us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.350s 77.510us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.650s 5.445us 0 1 0.00
clkmgr_csr_aliasing 0.860s 7.299us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.820s 14.815us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.920s 38.822us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.950s 42.556us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.940s 26.505us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.720s 5.564us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.680s 13.203us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.720s 5.564us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.710s 8.236us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.920s 28.503us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 6.170s 526.088us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 6.170s 526.088us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.480s 124.911us 1 1 100.00
clkmgr_csr_rw 0.650s 5.445us 0 1 0.00
clkmgr_csr_aliasing 0.860s 7.299us 0 1 0.00
clkmgr_same_csr_outstanding 0.760s 6.323us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.480s 124.911us 1 1 100.00
clkmgr_csr_rw 0.650s 5.445us 0 1 0.00
clkmgr_csr_aliasing 0.860s 7.299us 0 1 0.00
clkmgr_same_csr_outstanding 0.760s 6.323us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 2.830s 237.118us 0 1 0.00
clkmgr_tl_intg_err 0.700s 21.717us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 43.431us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 43.431us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 43.431us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 43.431us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.720s 12.056us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.700s 21.717us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.720s 5.564us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.680s 13.203us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 43.431us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.400s 95.421us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.650s 5.445us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 2.830s 237.118us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.650s 5.445us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.650s 5.445us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 2.830s 237.118us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.740s 11.698us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 5.210s 455.127us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 64615412321369019698326658534952551097318631680944175227375448756303072149191 76
UVM_INFO @ 5563561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 102415607416006673388447768065363677686489138317184448907212544957605848492941 198
UVM_INFO @ 455127188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 26830160501591727832528415358993399469157285234495667339128994563202952935491 78
UVM_INFO @ 13203383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 26858405183072114072210292516567330979641751464456441130660696945201023221082 78
UVM_INFO @ 8235856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 88455972080300044480708688362877045977224804202953946691581975656437956784353 74
UVM_INFO @ 11697710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 87401268120256903607649672313109031646458695364283904240453056346458360266369 75
UVM_INFO @ 12055632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 44286215754657834304106912621344949016905415288294694909016689750943602810683 78
UVM_INFO @ 21717129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 82124581453261569762817115530113146134087672484162940396882216135676464768636 76
UVM_INFO @ 7298779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 63693841110195511811068340508630312285932199299420325958272385612333956839364 226
UVM_INFO @ 237118366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_csr_rw 9254906192782353701876585497774652791607856545667572788297758906587089408454 75
UVM_INFO @ 5444815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 65968755079641215797885223887504124216239840177473733190274245408582559191423 75
UVM_INFO @ 5871715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 81504646036790594511536482090568809065057781066180403675200367865549229149261 75
UVM_INFO @ 6323443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---