Simulation Results: csrng

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.35 %
  • code
  • 92.52 %
  • assert
  • 93.89 %
  • func
  • 69.64 %
  • block
  • 97.25 %
  • line
  • 97.90 %
  • branch
  • 93.09 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 21.425us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 52.544us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 18.307us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 10.000s 267.316us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 395.500us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 98.176us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 18.307us 1 1 100.00
csrng_csr_aliasing 5.000s 395.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
alerts 1 1 100.00
csrng_alert 6.000s 173.360us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 184.000s 20375.321us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 184.000s 20375.321us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 5.000s 119.145us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 33.307us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 1.000s 16.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 46.324us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 46.324us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 52.544us 1 1 100.00
csrng_csr_rw 1.000s 18.307us 1 1 100.00
csrng_csr_aliasing 5.000s 395.500us 1 1 100.00
csrng_same_csr_outstanding 3.000s 42.728us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 52.544us 1 1 100.00
csrng_csr_rw 1.000s 18.307us 1 1 100.00
csrng_csr_aliasing 5.000s 395.500us 1 1 100.00
csrng_same_csr_outstanding 3.000s 42.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 75.992us 1 1 100.00
csrng_tl_intg_err 4.000s 237.032us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 19.517us 1 1 100.00
csrng_csr_rw 1.000s 18.307us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 6.000s 173.360us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 5.000s 119.145us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
csrng_sec_cm 3.000s 75.992us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
csrng_sec_cm 3.000s 75.992us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
csrng_sec_cm 3.000s 75.992us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
csrng_sec_cm 3.000s 75.992us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
csrng_sec_cm 3.000s 75.992us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 6.000s 173.360us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 5.000s 119.145us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 6.000s 173.360us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 237.032us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
csrng_sec_cm 3.000s 75.992us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
csrng_sec_cm 3.000s 75.992us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 93.193us 1 1 100.00
csrng_err 2.000s 22.998us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job killed!
csrng_stress_all_with_rand_reset 84250098709719538980844872923447394716997574245206701684352772512520060710298 None