Simulation Results: dma

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.54 %
  • code
  • 92.17 %
  • assert
  • 95.97 %
  • func
  • 62.47 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 1255.289us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 1251.660us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 210.514us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 27.987us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 19.962us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 2613.588us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 81.024us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 90.774us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 19.962us 1 1 100.00
dma_csr_aliasing 3.000s 81.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 92.000s 4945.650us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 75.000s 14589.712us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 210.000s 87556.428us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 210.000s 87556.428us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 75.000s 14589.712us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 872.000s 72814.430us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 210.000s 87556.428us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 1687.271us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 176.000s 325688.311us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 13.369us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 13.014us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 769.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 769.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 27.987us 1 1 100.00
dma_csr_rw 2.000s 19.962us 1 1 100.00
dma_csr_aliasing 3.000s 81.024us 1 1 100.00
dma_same_csr_outstanding 2.000s 238.767us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 27.987us 1 1 100.00
dma_csr_rw 2.000s 19.962us 1 1 100.00
dma_csr_aliasing 3.000s 81.024us 1 1 100.00
dma_same_csr_outstanding 2.000s 238.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 15.000s 759.732us 1 1 100.00
dma_generic_stress 872.000s 72814.430us 1 1 100.00
dma_handshake_stress 210.000s 87556.428us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 649.218us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 100.196us 1 1 100.00
dma_sec_cm 1.000s 26.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 69.000s 12287.240us 1 1 100.00
dma_longer_transfer 2.000s 377.791us 1 1 100.00
dma_stress_all_with_rand_reset 10.000s 367.600us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 115760432325061034444463719152052433411051328855563352238030449547940571066777 129
UVM_INFO @ 367599809ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---