Simulation Results: edn/edn1

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.65 %
  • code
  • 81.44 %
  • assert
  • 97.14 %
  • func
  • 78.36 %
  • line
  • 98.03 %
  • branch
  • 93.29 %
  • cond
  • 87.23 %
  • toggle
  • 86.59 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 33.649us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.980s 64.104us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 28.425us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.080s 1255.765us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.330s 41.401us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.350s 39.418us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 28.425us 1 1 100.00
edn_csr_aliasing 1.330s 41.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.980s 51.524us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.980s 51.524us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.980s 51.524us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.870s 19.846us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.120s 41.889us 1 1 100.00
errs 1 1 100.00
edn_err 0.950s 25.192us 1 1 100.00
disable 2 2 100.00
edn_disable 0.860s 21.364us 1 1 100.00
edn_disable_auto_req_mode 1.060s 105.034us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.910s 201.576us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.820s 95.246us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.990s 32.502us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.590s 23.250us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.590s 23.250us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.980s 64.104us 1 1 100.00
edn_csr_rw 0.830s 28.425us 1 1 100.00
edn_csr_aliasing 1.330s 41.401us 1 1 100.00
edn_same_csr_outstanding 1.100s 41.780us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.980s 64.104us 1 1 100.00
edn_csr_rw 0.830s 28.425us 1 1 100.00
edn_csr_aliasing 1.330s 41.401us 1 1 100.00
edn_same_csr_outstanding 1.100s 41.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.340s 1237.533us 1 1 100.00
edn_tl_intg_err 2.200s 140.893us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.210s 52.390us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.120s 41.889us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.340s 1237.533us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.340s 1237.533us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.340s 1237.533us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.340s 1237.533us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.120s 41.889us 1 1 100.00
edn_sec_cm 3.340s 1237.533us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.120s 41.889us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.200s 140.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 18.380s 1234.838us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 99178237793645148775883693086155379584912084795087862179826318775689982538233 137
UVM_INFO @ 1234838153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---