| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.070s | 59.609us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.210s | 256.952us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.150s | 72.404us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.130s | 53.607us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.920s | 19.933us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.770s | 71.898us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 4.370s | 288.954us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 2.060s | 157.769us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 0.880s | 81.654us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.770s | 71.898us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 2.060s | 157.769us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.300s | 150.855us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.100s | 208.197us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.980s | 264.125us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.270s | 76.902us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 1.740s | 51.214us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 2.950s | 170.530us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 6.300s | 171.118us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 1.770s | 43.662us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 1.050s | 358.341us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 13.010s | 6342.913us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.680s | 11.459us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.660s | 50.215us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.220s | 76.435us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 1.220s | 76.435us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.770s | 71.898us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.980s | 117.267us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 2.060s | 157.769us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.920s | 19.933us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.770s | 71.898us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.980s | 117.267us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 2.060s | 157.769us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.920s | 19.933us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 1.380s | 76.761us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 1.090s | 530.964us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 1.380s | 76.761us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.680s | 44.651us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 0.940s | 9.902us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 0.700s | 20.340us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| gpio_stress_all | 76612631562581913620418001006942988571939963485567356612784373628038525602259 | 463 |
UVM_INFO @ 6342913195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) | ||||
| gpio_stress_all_with_rand_reset | 29908199346914279765730173342980760881276953246638917157061099981555186874935 | 80 |
UVM_INFO @ 9901883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|