Simulation Results: hmac

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.82 %
  • code
  • 97.94 %
  • assert
  • 96.70 %
  • func
  • 44.82 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.40 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.290s 2112.998us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.770s 52.126us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.770s 25.307us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.190s 6518.497us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.360s 61.544us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 18.190s 7922.436us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.770s 25.307us 1 1 100.00
hmac_csr_aliasing 2.360s 61.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 90.800s 6121.039us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 71.020s 5278.393us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 208.290s 8365.023us 1 1 100.00
hmac_test_sha384_vectors 21.650s 1600.001us 1 1 100.00
hmac_test_sha512_vectors 21.760s 873.355us 1 1 100.00
hmac_test_hmac256_vectors 10.540s 296.432us 1 1 100.00
hmac_test_hmac384_vectors 8.520s 1094.368us 1 1 100.00
hmac_test_hmac512_vectors 12.820s 640.220us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.900s 1062.076us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 108.850s 4628.195us 1 1 100.00
error 1 1 100.00
hmac_error 4.720s 759.408us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 24.800s 1021.278us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.290s 2112.998us 1 1 100.00
hmac_long_msg 90.800s 6121.039us 1 1 100.00
hmac_back_pressure 71.020s 5278.393us 1 1 100.00
hmac_datapath_stress 108.850s 4628.195us 1 1 100.00
hmac_burst_wr 9.900s 1062.076us 1 1 100.00
hmac_stress_all 29.190s 3389.602us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.290s 2112.998us 1 1 100.00
hmac_long_msg 90.800s 6121.039us 1 1 100.00
hmac_back_pressure 71.020s 5278.393us 1 1 100.00
hmac_datapath_stress 108.850s 4628.195us 1 1 100.00
hmac_wipe_secret 24.800s 1021.278us 1 1 100.00
hmac_test_sha256_vectors 208.290s 8365.023us 1 1 100.00
hmac_test_sha384_vectors 21.650s 1600.001us 1 1 100.00
hmac_test_sha512_vectors 21.760s 873.355us 1 1 100.00
hmac_test_hmac256_vectors 10.540s 296.432us 1 1 100.00
hmac_test_hmac384_vectors 8.520s 1094.368us 1 1 100.00
hmac_test_hmac512_vectors 12.820s 640.220us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.290s 2112.998us 1 1 100.00
hmac_long_msg 90.800s 6121.039us 1 1 100.00
hmac_back_pressure 71.020s 5278.393us 1 1 100.00
hmac_datapath_stress 108.850s 4628.195us 1 1 100.00
hmac_burst_wr 9.900s 1062.076us 1 1 100.00
hmac_error 4.720s 759.408us 1 1 100.00
hmac_wipe_secret 24.800s 1021.278us 1 1 100.00
hmac_test_sha256_vectors 208.290s 8365.023us 1 1 100.00
hmac_test_sha384_vectors 21.650s 1600.001us 1 1 100.00
hmac_test_sha512_vectors 21.760s 873.355us 1 1 100.00
hmac_test_hmac256_vectors 10.540s 296.432us 1 1 100.00
hmac_test_hmac384_vectors 8.520s 1094.368us 1 1 100.00
hmac_test_hmac512_vectors 12.820s 640.220us 1 1 100.00
hmac_stress_all 29.190s 3389.602us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 29.190s 3389.602us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.580s 20.183us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.670s 12.615us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.970s 2035.069us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.970s 2035.069us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.770s 52.126us 1 1 100.00
hmac_csr_rw 0.770s 25.307us 1 1 100.00
hmac_csr_aliasing 2.360s 61.544us 1 1 100.00
hmac_same_csr_outstanding 2.800s 826.791us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.770s 52.126us 1 1 100.00
hmac_csr_rw 0.770s 25.307us 1 1 100.00
hmac_csr_aliasing 2.360s 61.544us 1 1 100.00
hmac_same_csr_outstanding 2.800s 826.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.850s 258.970us 1 1 100.00
hmac_tl_intg_err 2.710s 618.670us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.710s 618.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.290s 2112.998us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.640s 815.603us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 261.910s 20306.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.160s 42.991us 1 1 100.00