Simulation Results: kmac/unmasked

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.04 %
  • code
  • 87.97 %
  • assert
  • 95.80 %
  • func
  • 92.35 %
  • line
  • 97.14 %
  • branch
  • 94.71 %
  • cond
  • 90.99 %
  • toggle
  • 100.00 %
  • FSM
  • 57.02 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 50.410s 8164.421us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.140s 22.694us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.130s 42.575us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.500s 1800.733us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.980s 202.878us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.470s 43.763us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.130s 42.575us 1 1 100.00
kmac_csr_aliasing 3.980s 202.878us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.810s 36.385us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.030s 17.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 254.460s 23511.220us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 269.740s 3907.741us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1298.690s 74343.483us 1 1 100.00
kmac_test_vectors_sha3_256 1137.810s 17393.708us 1 1 100.00
kmac_test_vectors_sha3_384 23.810s 6963.919us 1 1 100.00
kmac_test_vectors_sha3_512 767.080s 46265.729us 1 1 100.00
kmac_test_vectors_shake_128 123.030s 3601.044us 1 1 100.00
kmac_test_vectors_shake_256 100.410s 58456.896us 1 1 100.00
kmac_test_vectors_kmac 1.950s 176.933us 1 1 100.00
kmac_test_vectors_kmac_xof 1.920s 67.667us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 245.590s 8821.788us 1 1 100.00
app 1 1 100.00
kmac_app 152.510s 10450.250us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 39.540s 18116.871us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 164.440s 9310.173us 1 1 100.00
error 1 1 100.00
kmac_error 282.270s 29372.508us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.340s 458.474us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 43.920s 10113.811us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 6.750s 245.666us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 6.590s 122.798us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 11.550s 1730.513us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.470s 38.902us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 449.330s 82300.709us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.900s 15.387us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.120s 26.951us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.850s 33.828us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.850s 33.828us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.140s 22.694us 1 1 100.00
kmac_csr_rw 1.130s 42.575us 1 1 100.00
kmac_csr_aliasing 3.980s 202.878us 1 1 100.00
kmac_same_csr_outstanding 1.350s 338.041us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.140s 22.694us 1 1 100.00
kmac_csr_rw 1.130s 42.575us 1 1 100.00
kmac_csr_aliasing 3.980s 202.878us 1 1 100.00
kmac_same_csr_outstanding 1.350s 338.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.370s 180.246us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.370s 180.246us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.370s 180.246us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.370s 180.246us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.330s 160.075us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 25.940s 2841.747us 1 1 100.00
kmac_tl_intg_err 2.370s 152.828us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.370s 152.828us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.470s 38.902us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 50.410s 8164.421us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 245.590s 8821.788us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.370s 180.246us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 25.940s 2841.747us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 25.940s 2841.747us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 25.940s 2841.747us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 50.410s 8164.421us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.470s 38.902us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 25.940s 2841.747us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 177.910s 157966.099us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 50.410s 8164.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 39.240s 8547.693us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 113832744183921366981087049589728755632971544048365581541746799215046298435955 86
UVM_INFO @ 10113811312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 98238145584384152621064930319844010617094427771787817878172137662193569085292 215
UVM_INFO @ 8547693319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---