Simulation Results: lc_ctrl/volatile_unlock_disabled

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.32 %
  • code
  • 85.87 %
  • assert
  • 95.99 %
  • func
  • 92.09 %
  • line
  • 97.80 %
  • branch
  • 96.34 %
  • cond
  • 79.84 %
  • toggle
  • 89.90 %
  • FSM
  • 65.45 %
Validation stages
V1
100.00%
V2
96.67%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 5.410s 758.884us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.860s 17.249us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 20.435us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.970s 47.157us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 26.930us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.300s 24.877us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 20.435us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 26.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.640s 153.255us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.300s 1221.056us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.950s 42.292us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.790s 94.572us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.440s 2656.798us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_prog_failure 3.790s 94.572us 1 1 100.00
lc_ctrl_errors 8.440s 2656.798us 1 1 100.00
lc_ctrl_security_escalation 5.930s 222.692us 1 1 100.00
lc_ctrl_jtag_state_failure 19.020s 3177.529us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.750s 2182.547us 1 1 100.00
lc_ctrl_jtag_errors 11.250s 1001.901us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.220s 260.975us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.240s 980.810us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.750s 2182.547us 1 1 100.00
lc_ctrl_jtag_errors 11.250s 1001.901us 1 1 100.00
lc_ctrl_jtag_access 1.040s 51.320us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.600s 1300.246us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.120s 89.330us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.850s 110.641us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.490s 910.186us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.940s 1290.889us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.820s 52.208us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.590s 405.719us 1 1 100.00
lc_ctrl_jtag_alert_test 0.910s 36.175us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.690s 93.079us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.870s 48.025us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 316.870s 16782.245us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.160s 84.487us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.890s 50.992us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.890s 50.992us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 17.249us 1 1 100.00
lc_ctrl_csr_rw 1.000s 20.435us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 26.930us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 45.979us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 17.249us 1 1 100.00
lc_ctrl_csr_rw 1.000s 20.435us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 26.930us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 45.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 907.037us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 907.037us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.300s 1221.056us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 4.180s 68.653us 0 1 0.00
lc_ctrl_sec_cm 6.740s 123.363us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.930s 222.692us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.640s 153.255us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.240s 980.810us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.590s 310.269us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.590s 310.269us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.020s 419.725us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.480s 350.891us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.480s 350.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 10.950s 8246.367us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
lc_ctrl_state_failure 114856307575116011032577427361597838836791519437756364361933934153748512892054 182
UVM_INFO @ 68653469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---