Simulation Results: lc_ctrl/volatile_unlock_enabled

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.23 %
  • code
  • 85.25 %
  • assert
  • 95.99 %
  • func
  • 92.45 %
  • line
  • 97.66 %
  • branch
  • 95.80 %
  • cond
  • 78.99 %
  • toggle
  • 88.37 %
  • FSM
  • 65.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.470s 175.702us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.050s 70.735us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 14.793us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.930s 246.297us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 121.769us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.060s 56.347us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 14.793us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 121.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.060s 256.887us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.740s 1125.475us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.840s 42.578us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.890s 321.631us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.420s 2024.300us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_prog_failure 1.890s 321.631us 1 1 100.00
lc_ctrl_errors 5.420s 2024.300us 1 1 100.00
lc_ctrl_security_escalation 6.570s 1199.889us 1 1 100.00
lc_ctrl_jtag_state_failure 62.680s 10835.536us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.330s 1497.978us 1 1 100.00
lc_ctrl_jtag_errors 39.640s 30026.645us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 9.130s 2156.567us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.890s 13926.525us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.330s 1497.978us 1 1 100.00
lc_ctrl_jtag_errors 39.640s 30026.645us 1 1 100.00
lc_ctrl_jtag_access 2.350s 977.385us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.200s 14496.220us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.740s 283.608us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.240s 488.036us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.860s 1057.184us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.940s 476.648us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.040s 118.798us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.620s 132.551us 1 1 100.00
lc_ctrl_jtag_alert_test 1.110s 96.414us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.130s 1899.641us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.230s 19.951us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 215.140s 40415.765us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.020s 24.826us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.780s 99.374us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.780s 99.374us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.050s 70.735us 1 1 100.00
lc_ctrl_csr_rw 0.830s 14.793us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 121.769us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 27.683us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.050s 70.735us 1 1 100.00
lc_ctrl_csr_rw 0.830s 14.793us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 121.769us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 27.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
lc_ctrl_tl_intg_err 1.680s 47.308us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.680s 47.308us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.740s 1125.475us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.490s 337.814us 1 1 100.00
lc_ctrl_sec_cm 6.240s 124.652us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.570s 1199.889us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.060s 256.887us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.890s 13926.525us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.790s 625.973us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.790s 625.973us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.210s 246.388us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.240s 506.986us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.240s 506.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 15.300s 3886.628us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 6937963024428029936512138253213377277975741126074073280349176684727689704927 223
UVM_INFO @ 3886628388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---