Simulation Results: mbx

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.09 %
  • code
  • 91.67 %
  • assert
  • 96.96 %
  • func
  • 84.63 %
  • block
  • 96.95 %
  • line
  • 96.91 %
  • branch
  • 92.07 %
  • toggle
  • 86.04 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 69.000s 16914.235us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 33.798us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 23.474us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 152.949us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 99.853us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 1.000s 17.202us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 23.474us 1 1 100.00
mbx_csr_aliasing 2.000s 99.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 5.000s 3991.747us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 90.000s 4894.435us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 35.000s 4645.797us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 1278.405us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 24.099us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 30.156us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 2.935us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 2.935us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 33.798us 1 1 100.00
mbx_csr_rw 1.000s 23.474us 1 1 100.00
mbx_csr_aliasing 2.000s 99.853us 1 1 100.00
mbx_same_csr_outstanding 2.000s 85.811us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 33.798us 1 1 100.00
mbx_csr_rw 1.000s 23.474us 1 1 100.00
mbx_csr_aliasing 2.000s 99.853us 1 1 100.00
mbx_same_csr_outstanding 2.000s 85.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 1.000s 266.609us 1 1 100.00
mbx_sec_cm 2.000s 13.425us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress 21931408464624815252084664948212768727381265796337982184245873158733759690460 473
UVM_INFO @ 3991746774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 108578785090481458262505672408441509819850255918911794306265552256445652195535 85
TL item was: req: (cip_tl_seq_item@16172) { a_addr: 'h6729ed0 a_data: 'h82c5dbf3 a_mask: 'hd a_size: 'h2 a_param: 'h0 a_source: 'h83 a_opcode: 'h1 a_user: 'h245fa d_param: 'h0 d_source: 'h83 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2935231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---