Simulation Results: otbn

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.12 %
  • code
  • 95.44 %
  • assert
  • 89.88 %
  • func
  • 97.03 %
  • block
  • 99.39 %
  • line
  • 99.58 %
  • branch
  • 92.33 %
  • toggle
  • 92.41 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 44.525us 1 1 100.00
single_binary 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 14.509us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 14.659us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 129.477us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 61.749us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 289.783us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 14.659us 1 1 100.00
otbn_csr_aliasing 4.000s 61.749us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 38.000s 1728.816us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 22.000s 928.074us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 17.000s 198.518us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 40.000s 158.142us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 136.000s 605.891us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 152.000s 1571.110us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 35.757us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 4.000s 8.752us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 57.618us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 214.823us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 24.337us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 162.213us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 162.213us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 14.509us 1 1 100.00
otbn_csr_rw 4.000s 14.659us 1 1 100.00
otbn_csr_aliasing 4.000s 61.749us 1 1 100.00
otbn_same_csr_outstanding 3.000s 55.720us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 14.509us 1 1 100.00
otbn_csr_rw 4.000s 14.659us 1 1 100.00
otbn_csr_aliasing 4.000s 61.749us 1 1 100.00
otbn_same_csr_outstanding 3.000s 55.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 91.798us 1 1 100.00
otbn_dmem_err 21.000s 127.227us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 201.146us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 59.986us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 216.270us 1 1 100.00
otbn_urnd_err 5.000s 7.145us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 34.083us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 35.947us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 83.455us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
otbn_tl_intg_err 9.000s 57.075us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 4.000s 4.464us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 44.525us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 21.000s 127.227us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 91.798us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 57.075us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 35.757us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 91.798us 1 1 100.00
otbn_dmem_err 21.000s 127.227us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 8.752us 0 1 0.00
otbn_illegal_mem_acc 6.000s 34.083us 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 91.798us 1 1 100.00
otbn_dmem_err 21.000s 127.227us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 8.752us 0 1 0.00
otbn_illegal_mem_acc 6.000s 34.083us 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 35.757us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 91.798us 1 1 100.00
otbn_dmem_err 21.000s 127.227us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 8.752us 0 1 0.00
otbn_illegal_mem_acc 6.000s 34.083us 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 219.922us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 71.805us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 17.000s 244.474us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 17.000s 244.474us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 62.242us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 109.125us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 50.311us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 50.311us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 9.453us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 136.000s 605.891us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 15.163us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 15.000s 48.529us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 527.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 175.000s 3912.168us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 36.861us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 58063280551922037739864036828704422125925848710385700255121137422691504724576 311
UVM_INFO @ 3912168489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 19522762208283929412693796417016322696304766091289663438192764087410419564942 105
UVM_INFO @ 8752254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 45349417357527418767893544786226159824476825737699460053573598623362503111948 108
UVM_INFO @ 7144991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 101771822779281310958063209443398431535722219284181094741656584763295132213445 86
UVM_INFO @ 4463748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---