Simulation Results: otp_ctrl

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.47 %
  • code
  • 71.14 %
  • assert
  • 89.67 %
  • func
  • 50.59 %
  • line
  • 87.33 %
  • branch
  • 82.41 %
  • cond
  • 85.12 %
  • toggle
  • 64.02 %
  • FSM
  • 36.84 %
Validation stages
V1
88.89%
V2
65.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.700s 110.326us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 10.840s 629.019us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.720s 1712.738us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.470s 86.980us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.200s 503.369us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 7.230s 213.398us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.040s 74.954us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.470s 86.980us 1 1 100.00
otp_ctrl_csr_aliasing 7.230s 213.398us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.590s 156.308us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.700s 572.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 142.830s 106386.568us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.390s 526.097us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 10.480s 1059.271us 0 1 0.00
otp_ctrl_check_fail 3.400s 203.899us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.630s 348.635us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 8.010s 611.773us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 8.760s 1319.791us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 6.520s 503.879us 1 1 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 52.080s 20005.824us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 29.190s 2691.950us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 10.500s 1115.235us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 19.880s 2729.140us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.560s 85.817us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.390s 148.464us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.450s 296.936us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.450s 296.936us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.720s 1712.738us 1 1 100.00
otp_ctrl_csr_rw 1.470s 86.980us 1 1 100.00
otp_ctrl_csr_aliasing 7.230s 213.398us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.290s 59.091us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.720s 1712.738us 1 1 100.00
otp_ctrl_csr_rw 1.470s 86.980us 1 1 100.00
otp_ctrl_csr_aliasing 7.230s 213.398us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.290s 59.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
otp_ctrl_tl_intg_err 12.390s 3058.560us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.390s 3058.560us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 10.840s 629.019us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 10.840s 629.019us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
otp_ctrl_macro_errs 29.190s 2691.950us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
otp_ctrl_macro_errs 29.190s 2691.950us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 12.260s 1238.978us 1 1 100.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.390s 526.097us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.400s 203.899us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 8.010s 611.773us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 8.010s 611.773us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 8.010s 611.773us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 8.010s 611.773us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 8.010s 611.773us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 10.840s 629.019us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 8.010s 611.773us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 10.840s 629.019us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 142.740s 71799.880us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.630s 348.635us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 10.840s 629.019us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 10.840s 629.019us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 29.190s 2691.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 79.790s 21899.216us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 9.530s 631.929us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 22707400911365411913792711439280527652581481624414723498160178802588890500886 112605
UVM_INFO @ 106386567787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 4122365156978552697688801640050831392014386616297282159881724372059729599282 89
UVM_INFO @ 21899216488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 91948171574035079220059450873990371686254178483638701399211259943450323909281 7589
UVM_INFO @ 1059270559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 90675943297536383172146273506581393177748221861510776708637923883055802605446 5467
UVM_INFO @ 611773429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 115483579129780485234232390978953959870965451912722509774290898923880305416465 2470
UVM_INFO @ 1115235315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 88910324170549611174838008293102415802627719145150668051463024593714698492988 17848
UVM_INFO @ 2729139634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 71881774756929432655291866461601121085664013110236629386952347245598793058690 3308
UVM_INFO @ 203898854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1036118439057754267609976165964829661068663940661212766682210849902305110437 1186
UVM_INFO @ 631929165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_parallel_key_req 73633358186590309828788986204113730756082059545705047645603318917167891122372 6733
UVM_INFO @ 1319791084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 21178120500763963301503864659575757543701176590073764844191167120970373663702 960
UVM_INFO @ 71799879540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 20202980780035029495114064624528927653638158462090166436736212376373573539362 91
UVM_INFO @ 74953589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---