Simulation Results: rom_ctrl/64kb

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.51 %
  • code
  • 98.11 %
  • assert
  • 96.66 %
  • func
  • 94.75 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.22 %
  • toggle
  • 99.77 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 10.020s 1048.560us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.220s 2082.178us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.280s 212.302us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.190s 382.807us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.450s 534.984us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.970s 308.078us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.280s 212.302us 1 1 100.00
rom_ctrl_csr_aliasing 7.450s 534.984us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.700s 1339.513us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.190s 387.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.600s 404.169us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.500s 3497.374us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.170s 772.438us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.760s 727.678us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.560s 758.347us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.560s 758.347us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.220s 2082.178us 1 1 100.00
rom_ctrl_csr_rw 6.280s 212.302us 1 1 100.00
rom_ctrl_csr_aliasing 7.450s 534.984us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.810s 557.142us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.220s 2082.178us 1 1 100.00
rom_ctrl_csr_rw 6.280s 212.302us 1 1 100.00
rom_ctrl_csr_aliasing 7.450s 534.984us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.810s 557.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.210s 5398.489us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 228.130s 480.587us 1 1 100.00
rom_ctrl_tl_intg_err 96.200s 457.217us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 228.130s 480.587us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 228.130s 480.587us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 228.130s 480.587us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 228.130s 480.587us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 10.020s 1048.560us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 10.020s 1048.560us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 10.020s 1048.560us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 96.200s 457.217us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
rom_ctrl_kmac_err_chk 12.170s 772.438us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.030s 3287.705us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.210s 5398.489us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 228.130s 480.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 76.050s 3447.725us 1 1 100.00