Simulation Results: rv_dm/use_dmi_interface

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.52 %
  • code
  • 73.59 %
  • assert
  • 95.01 %
  • func
  • 48.96 %
  • line
  • 90.22 %
  • branch
  • 75.00 %
  • cond
  • 76.18 %
  • toggle
  • 70.32 %
  • FSM
  • 56.25 %
Validation stages
V1
96.30%
V2
69.57%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 1.260s 626.827us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 2.570s 511.670us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.080s 145.467us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 9.170s 8337.262us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 1.940s 1845.845us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 20.910s 10920.365us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 5.450s 7382.557us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 46.670s 44889.900us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 26.530s 103029.704us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.490s 495.123us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.090s 677.595us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.890s 128.970us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.830s 169.210us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.910s 95.506us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.390s 1369.396us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.880s 186.948us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.450s 456.714us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.490s 495.123us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.890s 625.722us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.340s 586.672us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.890s 128.970us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.800s 95.552us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.390s 194.182us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.790s 223.265us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 37.970s 1441.834us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 51.140s 16514.179us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 2.440s 160.430us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 51.140s 16514.179us 1 1 100.00
rv_dm_csr_rw 1.790s 223.265us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.790s 68.229us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.900s 62.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 1.260s 626.827us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.610s 1077.424us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.690s 176.483us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.040s 518.302us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 2.420s 886.633us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 7.150s 4657.726us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 0.720s 84.670us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 1.200s 1339.693us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 0.880s 136.415us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.740s 338.644us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 2.110s 852.512us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.060s 754.783us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.750s 81.808us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 7.560s 3434.577us 1 1 100.00
rv_dm_tap_fsm_rand_reset 15.110s 1488.074us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 1.350s 394.042us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.890s 122.153us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.850s 76.064us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 3.270s 278.153us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 3.270s 278.153us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 51.140s 16514.179us 1 1 100.00
rv_dm_csr_hw_reset 1.390s 194.182us 1 1 100.00
rv_dm_csr_rw 1.790s 223.265us 1 1 100.00
rv_dm_same_csr_outstanding 3.380s 1112.032us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 51.140s 16514.179us 1 1 100.00
rv_dm_csr_hw_reset 1.390s 194.182us 1 1 100.00
rv_dm_csr_rw 1.790s 223.265us 1 1 100.00
rv_dm_same_csr_outstanding 3.380s 1112.032us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 1.510s 779.144us 1 1 100.00
rv_dm_tl_intg_err 23.430s 5651.533us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 23.430s 5651.533us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.110s 852.512us 1 1 100.00
rv_dm_debug_disabled 0.820s 42.756us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 2.110s 852.512us 1 1 100.00
rv_dm_debug_disabled 0.820s 42.756us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 1.260s 626.827us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 0.850s 252.287us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.910s 301.770us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.910s 301.770us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 0.850s 252.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 8.210s 7873.324us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 504.350s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:
rv_dm_sba_tl_access 15961626144930039495959621440398444896870546034603568749509206795142852354821 86
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5363
rv_dm_bad_sba_tl_access 13883181490338808469391598322077636785999844961475351427381091613945984642130 95
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @6679
Error-[CNST-CIF] Constraints inconsistency failure
rv_dm_delayed_resp_sba_tl_access 53803628375950108804027548071722683077279500267683036428295936838520624962121 133
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
rv_dm_autoincr_sba_tl_access 104835167562355279115350440570458478631711832962293193544438677374994861306296 133
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 32679341585979052926089826787259943658063598094029734013860475722289539694969 77
UVM_INFO @ 169210218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 20825241840803061311861935482392367650657182546990303939792616371796685473088 77
UVM_INFO @ 81807694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 44697410676955839790981135858152366946026917337389605287010799013968495126033 78
UVM_INFO @ 122153459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 112391098130012479099917419991095117444916903311662768158967256665346910047933 77
UVM_INFO @ 338643561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 97153922630177388821855769642984013741589927937950994499154976287191024947882 101
UVM_INFO @ 7873324392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_scanmode 115061344951719896810234819017902845547581692902971233625500969815281325984648 77
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---