Simulation Results: rv_timer

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.18 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 79.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.640s 124.957us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.630s 23.799us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.640s 14.008us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.060s 500.306us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.770s 35.679us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.730s 121.132us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.640s 14.008us 1 1 100.00
rv_timer_csr_aliasing 0.770s 35.679us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.800s 1544.748us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.620s 2534.638us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 7.730s 13141.523us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 7.730s 13141.523us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.760s 2378.378us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.630s 13.599us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.640s 14.764us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.650s 374.403us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.650s 374.403us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 23.799us 1 1 100.00
rv_timer_csr_rw 0.640s 14.008us 1 1 100.00
rv_timer_csr_aliasing 0.770s 35.679us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 71.655us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 23.799us 1 1 100.00
rv_timer_csr_rw 0.640s 14.008us 1 1 100.00
rv_timer_csr_aliasing 0.770s 35.679us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 71.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.780s 129.906us 1 1 100.00
rv_timer_tl_intg_err 1.100s 338.073us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.100s 338.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.980s 238.905us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 221.478us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 8.890s 3039.140us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 78217409596875911921172665916313280175170444775219376278898023049473835477847 76
UVM_INFO @ 238904692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 56982044080672556423474495157805243336345642481564558954647680422518905603781 75
UVM_INFO @ 1544747511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*])
rv_timer_max 64523151125220985252006670704566263710437894247444799525887437353206263423664 75
UVM_INFO @ 221478126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---