Simulation Results: spi_device/1r1w

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.88 %
  • code
  • 93.25 %
  • assert
  • 94.64 %
  • func
  • 57.74 %
  • line
  • 98.99 %
  • branch
  • 98.16 %
  • cond
  • 96.21 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 39.480s 6299.091us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.410s 22.179us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.110s 95.515us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 10.370s 10040.767us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.920s 306.472us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.450s 82.020us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.110s 95.515us 1 1 100.00
spi_device_csr_aliasing 14.920s 306.472us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.710s 18.259us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.470s 67.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.710s 15.531us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.640s 38.963us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.810s 13.275us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.030s 80.517us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.030s 80.517us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.690s 695.729us 1 1 100.00
spi_device_tpm_sts_read 1.030s 101.493us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 4.330s 531.922us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.480s 431.267us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 18.690s 9984.783us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 18.690s 9984.783us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.030s 442.592us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.030s 442.592us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.030s 442.592us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.030s 442.592us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.030s 442.592us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.340s 519.838us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.780s 103.077us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.780s 103.077us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.780s 103.077us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 17.360s 8334.861us 1 1 100.00
spi_device_read_buffer_direct 3.040s 728.601us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.780s 103.077us 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 9.470s 6420.404us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.490s 191.559us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.490s 191.559us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 39.480s 6299.091us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 68.100s 131315.540us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 107.290s 75346.787us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.850s 38.668us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.710s 12.843us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.260s 3090.750us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.260s 3090.750us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.410s 22.179us 1 1 100.00
spi_device_csr_rw 2.110s 95.515us 1 1 100.00
spi_device_csr_aliasing 14.920s 306.472us 1 1 100.00
spi_device_same_csr_outstanding 3.790s 220.482us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.410s 22.179us 1 1 100.00
spi_device_csr_rw 2.110s 95.515us 1 1 100.00
spi_device_csr_aliasing 14.920s 306.472us 1 1 100.00
spi_device_same_csr_outstanding 3.790s 220.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.260s 177.617us 1 1 100.00
spi_device_tl_intg_err 6.610s 1390.203us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.610s 1390.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 26.050s 2124.762us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 40605455768992708908762057555569506357268377845876976600670355679432580881884 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 24163453 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 24163453 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[970])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 102252735768303924978356278720304094975937026227500855742903384254773679355048 76
UVM_ERROR @ 11081218 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x569214 [10101101001001000010100] vs 0x0 [0])
UVM_ERROR @ 11083218 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1c783 [11100011110000011] vs 0x0 [0])
UVM_ERROR @ 11089218 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6d7b09 [11011010111101100001001] vs 0x0 [0])
UVM_ERROR @ 11108218 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf4412a [111101000100000100101010] vs 0x0 [0])