Simulation Results: sram_ctrl/main

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.47 %
  • code
  • 95.42 %
  • assert
  • 96.19 %
  • func
  • 91.80 %
  • block
  • 94.32 %
  • line
  • 94.81 %
  • branch
  • 90.76 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 370.094us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 67.575us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 28.521us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 50.344us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.925us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 3866.529us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 28.521us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.925us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 90.000s 2959.179us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 44.000s 2366.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 798.046us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 166.000s 22063.731us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 132.000s 9531.488us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 36.000s 60236.700us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 11.000s 5236.760us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 14.000s 4457.483us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 355.569us 1 1 100.00
sram_ctrl_partial_access_b2b 408.000s 496575.675us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 4755.027us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 3153.372us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 705.881us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 3721.196us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 684.930us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 264.000s 17889.306us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 35.427us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 62.161us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 62.161us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 67.575us 1 1 100.00
sram_ctrl_csr_rw 2.000s 28.521us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.925us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 13.444us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 67.575us 1 1 100.00
sram_ctrl_csr_rw 2.000s 28.521us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 15.925us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 13.444us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 7317.197us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 533.865us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 189.432us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 533.865us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 189.432us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 3721.196us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 3721.196us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 28.521us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 14.000s 4457.483us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 14.000s 4457.483us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 14.000s 4457.483us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 11.000s 5236.760us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 683.666us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 21.000s 7317.197us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 1388.227us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 370.094us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 370.094us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 14.000s 4457.483us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 533.865us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 11.000s 5236.760us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 533.865us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 533.865us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 370.094us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 533.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 5.000s 761.250us 1 1 100.00