Simulation Results: uart

 
28/04/2026 19:39:18 DVSim: v1.32.0 sha: 53d03cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.74 %
  • code
  • 96.65 %
  • assert
  • 97.12 %
  • func
  • 57.45 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.43 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.340s 459.812us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.680s 36.419us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 27.760us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.990s 457.043us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.890s 29.042us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.900s 254.946us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 27.760us 1 1 100.00
uart_csr_aliasing 0.890s 29.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 63.730s 43879.477us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.340s 459.812us 1 1 100.00
uart_tx_rx 63.730s 43879.477us 1 1 100.00
parity_error 2 2 100.00
uart_intr 57.870s 49613.070us 1 1 100.00
uart_rx_parity_err 21.690s 36863.685us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 63.730s 43879.477us 1 1 100.00
uart_intr 57.870s 49613.070us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 110.600s 113652.599us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 239.630s 178927.772us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 24.750s 19638.553us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 57.870s 49613.070us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 57.870s 49613.070us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 57.870s 49613.070us 1 1 100.00
perf 1 1 100.00
uart_perf 171.240s 12335.821us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.490s 3292.298us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.490s 3292.298us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.560s 1708.330us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 44.610s 45887.355us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.100s 391.716us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 13.920s 4429.300us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 457.850s 96103.356us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 565.930s 419091.319us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.650s 11.476us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.640s 70.687us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.980s 577.512us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.980s 577.512us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.680s 36.419us 1 1 100.00
uart_csr_rw 0.610s 27.760us 1 1 100.00
uart_csr_aliasing 0.890s 29.042us 1 1 100.00
uart_same_csr_outstanding 0.660s 91.559us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.680s 36.419us 1 1 100.00
uart_csr_rw 0.610s 27.760us 1 1 100.00
uart_csr_aliasing 0.890s 29.042us 1 1 100.00
uart_same_csr_outstanding 0.660s 91.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.050s 90.852us 1 1 100.00
uart_tl_intg_err 0.940s 58.863us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.940s 58.863us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 30.190s 10746.458us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *
uart_noise_filter 21232948056117769845157102638636411507920204666992645137117126042622628574445 74
UVM_ERROR @ 129893225 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 129893225 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 378238177 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 378238177 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_stress_all_with_rand_reset 21550081081820651569994696253679627133112543038432488377700806556767909309751 88
UVM_ERROR @ 844920327 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 846003669 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 846003669 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 942379440 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1