Simulation Results: aes/masked

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.06 %
  • code
  • 95.70 %
  • assert
  • 98.29 %
  • func
  • 64.20 %
  • block
  • 95.88 %
  • line
  • 97.51 %
  • branch
  • 89.82 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 153.262us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 164.273us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 91.173us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 66.161us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 190.113us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 112.770us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 59.763us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 66.161us 1 1 100.00
aes_csr_aliasing 2.000s 112.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 164.273us 1 1 100.00
aes_config_error 3.000s 183.234us 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 164.273us 1 1 100.00
aes_config_error 3.000s 183.234us 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 82.490us 1 1 100.00
aes_b2b 8.000s 226.459us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 164.273us 1 1 100.00
aes_config_error 3.000s 183.234us 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
aes_alert_reset 52.000s 10016.808us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 74.114us 1 1 100.00
aes_config_error 3.000s 183.234us 1 1 100.00
aes_alert_reset 52.000s 10016.808us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 139.696us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 16.000s 944.047us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 3214.444us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 52.000s 10016.808us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 82.490us 1 1 100.00
aes_sideload 3.000s 197.548us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 88.479us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 49.000s 10014.450us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 179.454us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 63.307us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 87.837us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 87.837us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 91.173us 1 1 100.00
aes_csr_rw 1.000s 66.161us 1 1 100.00
aes_csr_aliasing 2.000s 112.770us 1 1 100.00
aes_same_csr_outstanding 2.000s 63.476us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 91.173us 1 1 100.00
aes_csr_rw 1.000s 66.161us 1 1 100.00
aes_csr_aliasing 2.000s 112.770us 1 1 100.00
aes_same_csr_outstanding 2.000s 63.476us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 286.796us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_cipher_fi 2.000s 56.196us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 192.978us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 192.978us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 192.978us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 192.978us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 200.622us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 821.495us 1 1 100.00
aes_tl_intg_err 3.000s 239.975us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 239.975us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 52.000s 10016.808us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 192.978us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 192.978us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 164.273us 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
aes_alert_reset 52.000s 10016.808us 0 1 0.00
aes_core_fi 4.000s 496.116us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 179.454us 1 1 100.00
aes_config_error 3.000s 183.234us 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
aes_core_fi 4.000s 496.116us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 192.978us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 57.467us 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 82.490us 1 1 100.00
aes_sideload 3.000s 197.548us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 57.467us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 57.467us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 57.467us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 57.467us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 57.467us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 82.490us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 35.000s 10075.823us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_cipher_fi 2.000s 56.196us 1 1 100.00
aes_ctr_fi 2.000s 62.631us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 35.000s 10075.823us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_cipher_fi 2.000s 56.196us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 56.196us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 35.000s 10075.823us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_ctr_fi 2.000s 62.631us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 35.000s 10075.823us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_cipher_fi 2.000s 56.196us 1 1 100.00
aes_ctr_fi 2.000s 62.631us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 52.000s 10016.808us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_cipher_fi 2.000s 56.196us 1 1 100.00
aes_ctr_fi 2.000s 62.631us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_cipher_fi 2.000s 56.196us 1 1 100.00
aes_ctr_fi 2.000s 62.631us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_ctr_fi 2.000s 62.631us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 35.000s 10075.823us 0 1 0.00
aes_ghash_fi 3.000s 56.399us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 35.000s 10075.823us 0 1 0.00
aes_control_fi 2.000s 153.482us 1 1 100.00
aes_cipher_fi 2.000s 56.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
aes_stress_all_with_rand_reset 76.000s 25282.995us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 87446057007815952556124841828393815125491572287439942231888923542264217606198 3980
UVM_INFO @ 10016807600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 52603592070604427216650923734410245911302115871924300356051904832914491574316 1646
UVM_INFO @ 10014449803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 90154260184534410421119181942915704016502192598576480532745036144310922319430 2237
UVM_INFO @ 10075823436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---