Simulation Results: aes/unmasked

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.60 %
  • code
  • 90.81 %
  • assert
  • 97.57 %
  • func
  • 65.42 %
  • block
  • 90.85 %
  • line
  • 93.27 %
  • branch
  • 83.34 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.74%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 61.454us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 101.184us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 79.814us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 110.436us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 523.746us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 96.107us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 120.502us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 110.436us 1 1 100.00
aes_csr_aliasing 3.000s 96.107us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 101.184us 1 1 100.00
aes_config_error 2.000s 93.997us 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 101.184us 1 1 100.00
aes_config_error 2.000s 93.997us 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 69.562us 1 1 100.00
aes_b2b 3.000s 94.139us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 101.184us 1 1 100.00
aes_config_error 2.000s 93.997us 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
aes_alert_reset 21.000s 10009.911us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 56.283us 1 1 100.00
aes_config_error 2.000s 93.997us 1 1 100.00
aes_alert_reset 21.000s 10009.911us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 91.538us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 510.198us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 3.000s 198.738us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 21.000s 10009.911us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 69.562us 1 1 100.00
aes_sideload 2.000s 88.771us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 68.211us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 4.000s 216.072us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 162.429us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 115.533us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 61.771us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 61.771us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 79.814us 1 1 100.00
aes_csr_rw 1.000s 110.436us 1 1 100.00
aes_csr_aliasing 3.000s 96.107us 1 1 100.00
aes_same_csr_outstanding 2.000s 61.263us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 79.814us 1 1 100.00
aes_csr_rw 1.000s 110.436us 1 1 100.00
aes_csr_aliasing 3.000s 96.107us 1 1 100.00
aes_same_csr_outstanding 2.000s 61.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 81.770us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 72.672us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 238.215us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 238.215us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 238.215us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 238.215us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 198.390us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1169.314us 1 1 100.00
aes_tl_intg_err 2.000s 346.781us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 346.781us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 21.000s 10009.911us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 238.215us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 238.215us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 101.184us 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
aes_alert_reset 21.000s 10009.911us 0 1 0.00
aes_core_fi 2.000s 106.184us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 162.429us 1 1 100.00
aes_config_error 2.000s 93.997us 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
aes_core_fi 2.000s 106.184us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 238.215us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 85.462us 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 69.562us 1 1 100.00
aes_sideload 2.000s 88.771us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 85.462us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 85.462us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 85.462us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 85.462us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 85.462us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 69.562us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 25.000s 10014.425us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 72.672us 1 1 100.00
aes_ctr_fi 2.000s 67.718us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 25.000s 10014.425us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 72.672us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 72.672us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 25.000s 10014.425us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 67.718us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 25.000s 10014.425us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 72.672us 1 1 100.00
aes_ctr_fi 2.000s 67.718us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 21.000s 10009.911us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 72.672us 1 1 100.00
aes_ctr_fi 2.000s 67.718us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 72.672us 1 1 100.00
aes_ctr_fi 2.000s 67.718us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 67.718us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 25.000s 10014.425us 0 1 0.00
aes_ghash_fi 2.000s 55.916us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 25.000s 10014.425us 0 1 0.00
aes_control_fi 0.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 72.672us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 16.000s 1346.027us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 102409320459662896068218266178852393469781808845927462061638960538882056026696 1029
UVM_INFO @ 10009910992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 83646047362314756465360576767748335671459181057901482250082968440198923265860 612
UVM_INFO @ 10014425426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
aes_control_fi 115351460953813342066057935798391259010796570636397372839187952576472327090546 None
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 114860083572922658397083244625941919516880808291365117001156761990923162721790 1447
UVM_INFO @ 1346026720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---