Simulation Results: clkmgr

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.27 %
  • code
  • 68.40 %
  • assert
  • 88.84 %
  • func
  • 68.56 %
  • line
  • 81.50 %
  • branch
  • 86.40 %
  • cond
  • 77.04 %
  • toggle
  • 97.08 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.850s 81.670us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.090s 62.661us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.650s 3.473us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 2.390s 196.236us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.840s 13.751us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.750s 4.915us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.650s 3.473us 0 1 0.00
clkmgr_csr_aliasing 0.840s 13.751us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.880s 14.199us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.360s 155.607us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.940s 25.120us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.850s 81.670us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.670s 6.144us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.640s 6.202us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.670s 6.144us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.970s 143.986us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.200s 57.871us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.960s 314.264us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.960s 314.264us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.090s 62.661us 1 1 100.00
clkmgr_csr_rw 0.650s 3.473us 0 1 0.00
clkmgr_csr_aliasing 0.840s 13.751us 0 1 0.00
clkmgr_same_csr_outstanding 0.640s 4.010us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.090s 62.661us 1 1 100.00
clkmgr_csr_rw 0.650s 3.473us 0 1 0.00
clkmgr_csr_aliasing 0.840s 13.751us 0 1 0.00
clkmgr_same_csr_outstanding 0.640s 4.010us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.740s 8.928us 0 1 0.00
clkmgr_tl_intg_err 0.780s 8.528us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 72.395us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 72.395us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 72.395us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 72.395us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.690s 7.446us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.780s 8.528us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.670s 6.144us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.640s 6.202us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.440s 72.395us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.530s 92.918us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.650s 3.473us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.740s 8.928us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.650s 3.473us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.650s 3.473us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.740s 8.928us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.680s 3.967us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.680s 181.227us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 83269498468491008122278166638998877817302401319799082451123600445428125565146 75
UVM_INFO @ 6144253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 69796872398110928300804442397369921398535494311759569581573362123466437767452 77
UVM_INFO @ 181226969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 105541486690522581172615646617378000809740371176871948002923877191862780509258 76
UVM_INFO @ 143986369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 104106575175050283963285751626628427224219395583616595359240723240312795232174 78
UVM_INFO @ 6202189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 50002559712900066951692706631749580382340742742681782282300753042779155931571 74
UVM_INFO @ 3966737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 100416161653115970030141109625994819999387452402283896017443431236619065770699 75
UVM_INFO @ 7445836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 68945269897506709465697294473222362313681933448260877279194429380839860457512 75
UVM_INFO @ 3472971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 111068799038829857377337281688423546617913842713857710873232437078962087515825 83
UVM_INFO @ 8928130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_tl_intg_err 43562346182160266511692953003877190724206169797987067680026825719893320296648 86
UVM_INFO @ 8527797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 92445431295568964322720712992973490942079884021902576173359425582230162888413 76
UVM_INFO @ 13751049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 81457204815530606421484302441686705946799154252129642503879833057223583449871 76
UVM_INFO @ 4914644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 20618121758368603354183946964757013095988246745796267426693750755015099783407 75
UVM_INFO @ 196235724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 53091302945067932412075469106533411988545065662493081678114944790982043818180 75
UVM_INFO @ 4010225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---