Simulation Results: dma

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.38 %
  • code
  • 91.47 %
  • assert
  • 95.55 %
  • func
  • 60.11 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 265.069us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 233.802us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 321.935us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 16.535us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 54.717us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 2707.027us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 161.511us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 16.877us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 54.717us 1 1 100.00
dma_csr_aliasing 3.000s 161.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 43.000s 3505.181us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 244.000s 51234.189us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 314.000s 184466.257us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 314.000s 184466.257us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 244.000s 51234.189us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 70.000s 12871.070us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 314.000s 184466.257us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 2417.101us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 104.000s 38139.441us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 50.562us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 14.708us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 100.546us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 100.546us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 16.535us 1 1 100.00
dma_csr_rw 1.000s 54.717us 1 1 100.00
dma_csr_aliasing 3.000s 161.511us 1 1 100.00
dma_same_csr_outstanding 1.000s 25.549us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 16.535us 1 1 100.00
dma_csr_rw 1.000s 54.717us 1 1 100.00
dma_csr_aliasing 3.000s 161.511us 1 1 100.00
dma_same_csr_outstanding 1.000s 25.549us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 18.000s 97.291us 1 1 100.00
dma_generic_stress 70.000s 12871.070us 1 1 100.00
dma_handshake_stress 314.000s 184466.257us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 880.032us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 1305.908us 1 1 100.00
dma_sec_cm 1.000s 22.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 62.000s 6669.278us 1 1 100.00
dma_longer_transfer 8.000s 5542.032us 1 1 100.00
dma_stress_all_with_rand_reset 19.000s 1326.909us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 23371351519251181462506744059909754549437641452663946085386322330086805287735 122
UVM_INFO @ 1326909374ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---