Simulation Results: edn/edn0

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.33 %
  • code
  • 86.64 %
  • assert
  • 97.61 %
  • func
  • 80.75 %
  • line
  • 98.48 %
  • branch
  • 95.26 %
  • cond
  • 89.61 %
  • toggle
  • 95.02 %
  • FSM
  • 54.84 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.930s 19.003us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 64.919us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 79.484us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 995.775us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.970s 76.930us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.050s 44.413us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 79.484us 1 1 100.00
edn_csr_aliasing 0.970s 76.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.470s 68.718us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.470s 68.718us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.470s 68.718us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 23.582us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.130s 203.457us 1 1 100.00
errs 1 1 100.00
edn_err 0.740s 28.216us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 23.464us 1 1 100.00
edn_disable_auto_req_mode 0.950s 84.193us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.030s 185.432us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 15.725us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 33.913us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.100s 280.533us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.100s 280.533us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 64.919us 1 1 100.00
edn_csr_rw 0.750s 79.484us 1 1 100.00
edn_csr_aliasing 0.970s 76.930us 1 1 100.00
edn_same_csr_outstanding 0.910s 74.231us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 64.919us 1 1 100.00
edn_csr_rw 0.750s 79.484us 1 1 100.00
edn_csr_aliasing 0.970s 76.930us 1 1 100.00
edn_same_csr_outstanding 0.910s 74.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.470s 1066.252us 1 1 100.00
edn_tl_intg_err 1.960s 102.575us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 34.730us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.130s 203.457us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.470s 1066.252us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.470s 1066.252us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.470s 1066.252us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.470s 1066.252us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.130s 203.457us 1 1 100.00
edn_sec_cm 3.470s 1066.252us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.130s 203.457us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.960s 102.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 23.710s 22710.136us 1 1 100.00