Simulation Results: edn/edn1

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.67 %
  • code
  • 82.42 %
  • assert
  • 97.14 %
  • func
  • 80.46 %
  • line
  • 98.03 %
  • branch
  • 93.07 %
  • cond
  • 88.15 %
  • toggle
  • 87.42 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 69.245us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 34.326us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 13.852us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.400s 392.598us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.980s 42.921us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.070s 87.343us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 13.852us 1 1 100.00
edn_csr_aliasing 0.980s 42.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.110s 40.106us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.110s 40.106us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.110s 40.106us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.870s 22.738us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.970s 27.542us 1 1 100.00
errs 1 1 100.00
edn_err 0.810s 23.798us 1 1 100.00
disable 2 2 100.00
edn_disable 0.860s 46.211us 1 1 100.00
edn_disable_auto_req_mode 1.060s 41.516us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.930s 430.206us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 23.242us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 26.526us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.760s 44.564us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.760s 44.564us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 34.326us 1 1 100.00
edn_csr_rw 0.850s 13.852us 1 1 100.00
edn_csr_aliasing 0.980s 42.921us 1 1 100.00
edn_same_csr_outstanding 0.930s 62.165us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 34.326us 1 1 100.00
edn_csr_rw 0.850s 13.852us 1 1 100.00
edn_csr_aliasing 0.980s 42.921us 1 1 100.00
edn_same_csr_outstanding 0.930s 62.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.410s 1060.756us 1 1 100.00
edn_tl_intg_err 1.780s 84.752us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.760s 72.570us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.970s 27.542us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.410s 1060.756us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.410s 1060.756us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.410s 1060.756us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.410s 1060.756us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.970s 27.542us 1 1 100.00
edn_sec_cm 2.410s 1060.756us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.970s 27.542us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.780s 84.752us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 28.840s 6723.681us 1 1 100.00