Simulation Results: hmac

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.06 %
  • code
  • 97.28 %
  • assert
  • 96.70 %
  • func
  • 43.21 %
  • line
  • 99.69 %
  • branch
  • 99.17 %
  • cond
  • 96.35 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.340s 885.951us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.110s 17.714us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.940s 16.607us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.760s 3117.635us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.200s 263.474us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.440s 21.591us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.940s 16.607us 1 1 100.00
hmac_csr_aliasing 6.200s 263.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 8.930s 1165.406us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 44.170s 3965.374us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.710s 754.653us 1 1 100.00
hmac_test_sha384_vectors 21.890s 509.154us 1 1 100.00
hmac_test_sha512_vectors 326.080s 38539.699us 1 1 100.00
hmac_test_hmac256_vectors 10.110s 605.108us 1 1 100.00
hmac_test_hmac384_vectors 12.390s 1353.844us 1 1 100.00
hmac_test_hmac512_vectors 8.530s 2087.407us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.550s 88.982us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 177.980s 1262.079us 1 1 100.00
error 1 1 100.00
hmac_error 30.900s 9229.306us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 41.050s 4227.527us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.340s 885.951us 1 1 100.00
hmac_long_msg 8.930s 1165.406us 1 1 100.00
hmac_back_pressure 44.170s 3965.374us 1 1 100.00
hmac_datapath_stress 177.980s 1262.079us 1 1 100.00
hmac_burst_wr 3.550s 88.982us 1 1 100.00
hmac_stress_all 48.470s 5149.026us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.340s 885.951us 1 1 100.00
hmac_long_msg 8.930s 1165.406us 1 1 100.00
hmac_back_pressure 44.170s 3965.374us 1 1 100.00
hmac_datapath_stress 177.980s 1262.079us 1 1 100.00
hmac_wipe_secret 41.050s 4227.527us 1 1 100.00
hmac_test_sha256_vectors 8.710s 754.653us 1 1 100.00
hmac_test_sha384_vectors 21.890s 509.154us 1 1 100.00
hmac_test_sha512_vectors 326.080s 38539.699us 1 1 100.00
hmac_test_hmac256_vectors 10.110s 605.108us 1 1 100.00
hmac_test_hmac384_vectors 12.390s 1353.844us 1 1 100.00
hmac_test_hmac512_vectors 8.530s 2087.407us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.340s 885.951us 1 1 100.00
hmac_long_msg 8.930s 1165.406us 1 1 100.00
hmac_back_pressure 44.170s 3965.374us 1 1 100.00
hmac_datapath_stress 177.980s 1262.079us 1 1 100.00
hmac_burst_wr 3.550s 88.982us 1 1 100.00
hmac_error 30.900s 9229.306us 1 1 100.00
hmac_wipe_secret 41.050s 4227.527us 1 1 100.00
hmac_test_sha256_vectors 8.710s 754.653us 1 1 100.00
hmac_test_sha384_vectors 21.890s 509.154us 1 1 100.00
hmac_test_sha512_vectors 326.080s 38539.699us 1 1 100.00
hmac_test_hmac256_vectors 10.110s 605.108us 1 1 100.00
hmac_test_hmac384_vectors 12.390s 1353.844us 1 1 100.00
hmac_test_hmac512_vectors 8.530s 2087.407us 1 1 100.00
hmac_stress_all 48.470s 5149.026us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 48.470s 5149.026us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.700s 16.880us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.880s 62.607us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.750s 781.099us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.750s 781.099us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.110s 17.714us 1 1 100.00
hmac_csr_rw 0.940s 16.607us 1 1 100.00
hmac_csr_aliasing 6.200s 263.474us 1 1 100.00
hmac_same_csr_outstanding 1.740s 136.145us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.110s 17.714us 1 1 100.00
hmac_csr_rw 0.940s 16.607us 1 1 100.00
hmac_csr_aliasing 6.200s 263.474us 1 1 100.00
hmac_same_csr_outstanding 1.740s 136.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.110s 285.036us 1 1 100.00
hmac_tl_intg_err 1.930s 103.481us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.930s 103.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.340s 885.951us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.220s 188.493us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 15.020s 5044.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.620s 130.257us 1 1 100.00