Simulation Results: i2c

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.25 %
  • code
  • 81.65 %
  • assert
  • 96.19 %
  • func
  • 77.91 %
  • line
  • 96.41 %
  • branch
  • 92.33 %
  • cond
  • 85.23 %
  • toggle
  • 89.66 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
92.68%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 23.870s 2168.355us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 21.050s 919.851us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.800s 81.681us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.760s 27.255us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.330s 3725.105us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.270s 243.493us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.920s 71.846us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.760s 27.255us 1 1 100.00
i2c_csr_aliasing 1.270s 243.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.310s 47.883us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 833.400s 91495.042us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 1.620s 883.010us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.650s 117.784us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 134.300s 13187.833us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 38.340s 7190.791us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.210s 482.602us 1 1 100.00
i2c_host_fifo_fmt_empty 5.530s 875.684us 1 1 100.00
i2c_host_fifo_reset_rx 6.370s 956.869us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 105.810s 11124.492us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 11.210s 1752.593us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 3.600s 93.191us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.890s 383.945us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 138.990s 20558.668us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.130s 2098.389us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 11.580s 1445.415us 1 1 100.00
i2c_target_intr_smoke 4.590s 2720.662us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.310s 144.938us 1 1 100.00
i2c_target_fifo_reset_tx 1.120s 293.557us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 99.490s 28875.775us 1 1 100.00
i2c_target_stress_rd 11.580s 1445.415us 1 1 100.00
i2c_target_intr_stress_wr 6.150s 9104.895us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.290s 2738.346us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 81.540s 2555.775us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.150s 3168.121us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.920s 1201.096us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.810s 1148.370us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.400s 305.720us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 1.620s 883.010us 1 1 100.00
i2c_host_perf_precise 26.100s 2506.922us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 11.210s 1752.593us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 7.290s 899.475us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.800s 4669.122us 1 1 100.00
i2c_target_nack_acqfull_addr 2.150s 1026.010us 1 1 100.00
i2c_target_nack_txstretch 1.340s 2865.023us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 11.620s 2887.716us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.880s 466.129us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.870s 48.249us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.820s 22.701us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.710s 42.994us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.710s 42.994us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.800s 81.681us 1 1 100.00
i2c_csr_rw 0.760s 27.255us 1 1 100.00
i2c_csr_aliasing 1.270s 243.493us 1 1 100.00
i2c_same_csr_outstanding 1.190s 80.478us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.800s 81.681us 1 1 100.00
i2c_csr_rw 0.760s 27.255us 1 1 100.00
i2c_csr_aliasing 1.270s 243.493us 1 1 100.00
i2c_same_csr_outstanding 1.190s 80.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.110s 94.837us 1 1 100.00
i2c_sec_cm 1.440s 131.374us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.110s 94.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 41.080s 969.912us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.750s 701.735us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 2.980s 1037.037us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 13835155271704509864508743911981348364540952426740151787785579042734900577031 96
UVM_INFO @ 47882738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
i2c_host_stress_all 21662526774727600537907372513371404774339021378675612901118279385493474783384 140
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3338030
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 31199244492662058009754377534022490781123191252785389840479760536357239736639 84
UVM_INFO @ 383945435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 84488657570592040510196298500270493053382314063725603365639488568705851600282 78
UVM_INFO @ 701735278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 44282976470393573167853652843398226916164884898824007770497087845270089739489 107
UVM_INFO @ 969911621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 39331953959219644689201787722962317807829668052107423421371522452269617285707 83
UVM_INFO @ 1037036919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---