Simulation Results: kmac/unmasked

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.48 %
  • code
  • 88.63 %
  • assert
  • 97.75 %
  • func
  • 91.05 %
  • line
  • 97.20 %
  • branch
  • 94.71 %
  • cond
  • 93.47 %
  • toggle
  • 99.92 %
  • FSM
  • 57.85 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 25.670s 1473.607us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.260s 41.463us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.480s 151.929us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 9.870s 1536.346us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.040s 199.800us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.980s 29.846us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.480s 151.929us 1 1 100.00
kmac_csr_aliasing 5.040s 199.800us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.810s 18.448us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.320s 20.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 261.090s 8066.989us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 559.260s 35605.795us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 34.200s 2675.128us 1 1 100.00
kmac_test_vectors_sha3_256 29.690s 5984.782us 1 1 100.00
kmac_test_vectors_sha3_384 781.440s 51540.046us 1 1 100.00
kmac_test_vectors_sha3_512 812.990s 99332.630us 1 1 100.00
kmac_test_vectors_shake_128 1979.860s 371267.265us 1 1 100.00
kmac_test_vectors_shake_256 78.440s 1594.570us 1 1 100.00
kmac_test_vectors_kmac 1.770s 68.101us 1 1 100.00
kmac_test_vectors_kmac_xof 1.750s 50.913us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 322.130s 15376.626us 1 1 100.00
app 1 1 100.00
kmac_app 86.870s 4109.868us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 58.110s 57415.267us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 129.530s 11079.779us 1 1 100.00
error 1 1 100.00
kmac_error 63.310s 2280.844us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.600s 953.294us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 18.960s 10389.025us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 10.080s 610.408us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 5.340s 245.636us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 32.730s 16621.143us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.790s 69.493us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 283.600s 16738.367us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.850s 18.915us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.980s 40.780us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.840s 199.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.840s 199.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.260s 41.463us 1 1 100.00
kmac_csr_rw 1.480s 151.929us 1 1 100.00
kmac_csr_aliasing 5.040s 199.800us 1 1 100.00
kmac_same_csr_outstanding 3.000s 361.296us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.260s 41.463us 1 1 100.00
kmac_csr_rw 1.480s 151.929us 1 1 100.00
kmac_csr_aliasing 5.040s 199.800us 1 1 100.00
kmac_same_csr_outstanding 3.000s 361.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.790s 59.363us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.790s 59.363us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.790s 59.363us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.790s 59.363us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.350s 281.875us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 22.390s 1572.993us 1 1 100.00
kmac_tl_intg_err 3.270s 154.328us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.270s 154.328us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.790s 69.493us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 25.670s 1473.607us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 322.130s 15376.626us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.790s 59.363us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 22.390s 1572.993us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 22.390s 1572.993us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 22.390s 1572.993us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 25.670s 1473.607us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.790s 69.493us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 22.390s 1572.993us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 46.310s 4855.446us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 25.670s 1473.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 20.530s 5263.647us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 92028759786298152592245483565371069539752682968194133486718770099090674778790 85
UVM_INFO @ 10389025357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---