Simulation Results: lc_ctrl/volatile_unlock_disabled

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.02 %
  • code
  • 86.02 %
  • assert
  • 95.99 %
  • func
  • 94.06 %
  • line
  • 97.80 %
  • branch
  • 96.56 %
  • cond
  • 80.16 %
  • toggle
  • 88.29 %
  • FSM
  • 67.27 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.410s 210.821us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.780s 153.160us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.110s 27.628us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.480s 41.757us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.830s 110.340us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.250s 78.940us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.110s 27.628us 1 1 100.00
lc_ctrl_csr_aliasing 1.830s 110.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.440s 136.616us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.840s 254.127us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.740s 41.235us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.240s 59.547us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.420s 449.964us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_prog_failure 2.240s 59.547us 1 1 100.00
lc_ctrl_errors 9.420s 449.964us 1 1 100.00
lc_ctrl_security_escalation 5.990s 1059.094us 1 1 100.00
lc_ctrl_jtag_state_failure 22.540s 2562.064us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.390s 196.555us 1 1 100.00
lc_ctrl_jtag_errors 42.750s 10157.631us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.230s 433.321us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.030s 3160.842us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.390s 196.555us 1 1 100.00
lc_ctrl_jtag_errors 42.750s 10157.631us 1 1 100.00
lc_ctrl_jtag_access 5.940s 1251.972us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.760s 6829.258us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.840s 545.174us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.370s 363.250us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.300s 1511.323us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.290s 948.331us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.990s 241.114us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.960s 217.383us 1 1 100.00
lc_ctrl_jtag_alert_test 1.470s 275.441us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 30.700s 4864.837us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.800s 15.820us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 89.260s 37453.522us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.350s 466.665us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.580s 60.703us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.580s 60.703us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 153.160us 1 1 100.00
lc_ctrl_csr_rw 1.110s 27.628us 1 1 100.00
lc_ctrl_csr_aliasing 1.830s 110.340us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 269.978us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 153.160us 1 1 100.00
lc_ctrl_csr_rw 1.110s 27.628us 1 1 100.00
lc_ctrl_csr_aliasing 1.830s 110.340us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 269.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
lc_ctrl_tl_intg_err 2.540s 174.545us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.540s 174.545us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.840s 254.127us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.050s 981.199us 1 1 100.00
lc_ctrl_sec_cm 6.790s 943.212us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.990s 1059.094us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.440s 136.616us 1 1 100.00
lc_ctrl_jtag_state_post_trans 16.030s 3160.842us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.270s 320.422us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.270s 320.422us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.820s 2101.370us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.280s 880.247us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.280s 880.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.810s 575.675us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 38169105163497193485128163751431958914989296741704413108421015747341005877631 207
UVM_INFO @ 575675267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---