Simulation Results: lc_ctrl/volatile_unlock_enabled

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.08 %
  • code
  • 85.53 %
  • assert
  • 95.99 %
  • func
  • 91.73 %
  • line
  • 97.66 %
  • branch
  • 96.01 %
  • cond
  • 79.95 %
  • toggle
  • 88.56 %
  • FSM
  • 65.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.620s 62.704us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.320s 21.189us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.780s 41.721us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.590s 461.123us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 32.320us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.390s 130.126us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.780s 41.721us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 32.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.750s 411.112us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.570s 957.444us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 38.264us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.060s 356.259us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.600s 363.150us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_prog_failure 2.060s 356.259us 1 1 100.00
lc_ctrl_errors 4.600s 363.150us 1 1 100.00
lc_ctrl_security_escalation 6.590s 456.394us 1 1 100.00
lc_ctrl_jtag_state_failure 24.280s 9993.786us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.840s 1650.178us 1 1 100.00
lc_ctrl_jtag_errors 17.510s 6700.334us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.690s 909.856us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.420s 295.276us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.840s 1650.178us 1 1 100.00
lc_ctrl_jtag_errors 17.510s 6700.334us 1 1 100.00
lc_ctrl_jtag_access 2.670s 863.159us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 24.540s 5341.454us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.720s 118.144us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.240s 70.238us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.200s 2848.030us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.750s 714.593us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.210s 27.372us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.400s 193.196us 1 1 100.00
lc_ctrl_jtag_alert_test 2.160s 166.703us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.440s 1010.440us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.840s 49.586us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 98.770s 52435.480us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.230s 82.591us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.660s 46.385us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.660s 46.385us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.320s 21.189us 1 1 100.00
lc_ctrl_csr_rw 0.780s 41.721us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 32.320us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.110s 96.455us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.320s 21.189us 1 1 100.00
lc_ctrl_csr_rw 0.780s 41.721us 1 1 100.00
lc_ctrl_csr_aliasing 1.160s 32.320us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.110s 96.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
lc_ctrl_tl_intg_err 1.390s 56.129us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.390s 56.129us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.570s 957.444us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.000s 1435.348us 1 1 100.00
lc_ctrl_sec_cm 6.090s 118.619us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.590s 456.394us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.750s 411.112us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.420s 295.276us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.560s 307.991us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.560s 307.991us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.460s 708.209us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.290s 525.008us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.290s 525.008us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 18.590s 879.801us 1 1 100.00