| V1 |
|
83.33% |
| V2 |
|
72.73% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 79.000s | 7576.715us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 15.061us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 13.845us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 3.000s | 369.004us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 20.785us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 1.000s | 1.182us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 13.845us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 20.785us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 0 | 1 | 0.00 | |||
| mbx_stress | 9.000s | 2399.019us | 0 | 1 | 0.00 | |
| mbx_max_activity | 0 | 1 | 0.00 | |||
| mbx_stress_zero_delays | 2.000s | 112.806us | 0 | 1 | 0.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 35.000s | 27034.802us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 9.000s | 2777.528us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 30.165us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 1.000s | 58.293us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 1.000s | 17.720us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 1.000s | 17.720us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 15.061us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 13.845us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 20.785us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 16.023us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 1.000s | 15.061us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 13.845us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 20.785us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 16.023us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_tl_intg_err | 2.000s | 379.654us | 1 | 1 | 100.00 | |
| mbx_sec_cm | 1.000s | 22.549us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register | ||||
| mbx_stress | 41363948851750387175314630900334537134086614468962491925192510033944980045107 | 627 |
UVM_INFO @ 2399019246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_stress_zero_delays | 39778294461402642879530448304766322584894864977693340295147347882091981938397 | 89 |
UVM_INFO @ 112806189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). | ||||
| mbx_tl_errors | 21611258679317884132812644272026831002230408024843384041345345998691097884055 | 85 |
TL item was: req: (cip_tl_seq_item@15733) { a_addr: 'hc54080d4 a_data: 'h4dca1f6d a_mask: 'h1 a_size: 'h1 a_param: 'h0 a_source: 'h58 a_opcode: 'h1 a_user: 'h26625 d_param: 'h0 d_source: 'h58 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 17720008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_csr_mem_rw_with_rand_reset | 35263027381116588597041536502344147155266942891279911649576018784537904686724 | 86 |
TL item was: req: (cip_tl_seq_item@18709) { a_addr: 'h5aab7890 a_data: 'hcf1ed8bb a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'h4d a_opcode: 'h1 a_user: 'h26757 d_param: 'h0 d_source: 'h4d d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 1181978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|