Simulation Results: rom_ctrl/32kb

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.95 %
  • code
  • 97.86 %
  • assert
  • 96.80 %
  • func
  • 96.18 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.77 %
  • toggle
  • 99.49 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.030s 165.307us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.450s 547.360us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.590s 123.912us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.820s 298.625us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.120s 731.704us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.650s 214.300us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.590s 123.912us 1 1 100.00
rom_ctrl_csr_aliasing 3.120s 731.704us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.160s 167.417us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.170s 127.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.320s 140.989us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.470s 1492.728us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.950s 744.545us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.800s 125.509us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.560s 503.579us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.560s 503.579us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.450s 547.360us 1 1 100.00
rom_ctrl_csr_rw 3.590s 123.912us 1 1 100.00
rom_ctrl_csr_aliasing 3.120s 731.704us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.910s 959.794us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.450s 547.360us 1 1 100.00
rom_ctrl_csr_rw 3.590s 123.912us 1 1 100.00
rom_ctrl_csr_aliasing 3.120s 731.704us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.910s 959.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.640s 1090.611us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 193.230s 3189.477us 1 1 100.00
rom_ctrl_tl_intg_err 23.700s 430.886us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 193.230s 3189.477us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 193.230s 3189.477us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.230s 3189.477us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 193.230s 3189.477us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.030s 165.307us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.030s 165.307us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.030s 165.307us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.700s 430.886us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
rom_ctrl_kmac_err_chk 5.950s 744.545us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.460s 9746.861us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.640s 1090.611us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.230s 3189.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 51.900s 7845.530us 1 1 100.00